Texas Instruments Announcements Span the Processor Spectrum

Submitted by BDTI on Wed, 11/16/2011 - 19:00

Back in November 2010 at Electronica in Munich, Germany, Texas Instruments unveiled the TMS320C66x DSP family, then consisting of a quad-core communications SoC (the TMS320C6670) along with three pin-compatible conventional DSPs in two-, four- and eight-core variants (the TMS320C6672, TMS320C6674 and TMS320C6678), all based on the company's earlier-unveiled KeyStone architecture. At that same time, TI trumpeted its products' fixed- and floating-point performance results on the BDTI DSP Kernel Benchmarks suite, noting (for example) that "The score for the C66x DSP core on the floating-point category of the benchmark is more than two times higher than any previously benchmarked device." The eight-core TMS320C6678 runs up to 1.25 GHz, for 10 GHz cumulative DSP processing capabilities. Announced pricing for the C66x DSPs began at $99 (quantity 1,000) and product shipments began in early 2011. Also announced were two evaluation modules, the TMDXEVM6670L and TMDXEVM6678L, both costing $399 and including "a free MC-SDK [editor note: Multi-Core Software Development Kit], Code Composer Studio software and suite of application/demo codes to allow programmers to quickly come up to speed on the new platform."

Since that time, the TMS320C66x-related announcements have continued, albeit at a somewhat more muted pace and tenor. In late April, TI unveiled "a new multi-core software development kit (MCSDK), optimized multi-core software libraries, Linux kernel support for the C66x DSP generation, and support for the OpenMP Application Program Interface (API)." At that same time, the company rolled out the TMS320C6671, a 1.25 GHz single-core variant of the earlier-unveiled TMS320C6672, TMS320C6674 and TMS320C6678. For the TMS320C6670, there was "a new multistandard Bit Rate Coprocessor (BCP), as well as other coprocessors that accelerate physical layer processing for LTE, WCDMA, TD-SCDMA and WiMAX, substantially increasing system capacity and performance with low latency".

Device

# of C66x DSP cores

Speed options

Memory

Key peripherals

Key accelerators, coprocessors

TMS320C6670

4

1 GHz, 1.2 GHz

1 MByte L2 dedicated cache per core, 2 MByte shared L2 cache, DDR3-1600 MHz external DRAM I/F

Serial RapidIO V2.1 x4, PCI Express Gen II x2, Antenna Interface 2, Ethernet Subsystem, Open Base Station Architecture Initiative/Common Public Radio Interface x6

Packet Accelerator, Security Accelerator, Turbo Encoder/Decoder, Viterbi Decoders, FFT Coprocessor, Bit Rate Coprocessor, Receive Accelerator, Transmit Accelerator

TMS320C6671

1

1 GHz, 1.25 GHz

512 KByte L2 dedicated cache per core, 4 MByte shared L2 cache, DDR3-1600 MHz external DRAM I/F

Serial RapidIO V2.1 x4, PCI Express Gen II x2, Telephony Serial Interface Port x2, Ethernet Subsystem

Packet Accelerator, Security Accelerator

TMS320C6672

2

1 GHz, 1.25 GHz, 1.5 GHz

TMS320C6674

4

1 GHz, 1.25 GHz

TMS320C6678

8

1 GHz, 1.25 GHz

Table 1: The TMS320C66x product family.

TI also subsequently upped the peak clock speed on the dual-core TMS3206672 to 1.5 GHz. Table 1 shows the current configurations of the TMS320C66x family. Mid-October and early November brought application-focused press releases bereft any corresponding new chip or development tool news, the former release targeting potential customers in industrial automation applications and the latter targeting mission-critical designs. In-between them, however, in the context of a release focused on medical imaging applications, came a more tangible update, a "free medical imaging software toolkit (STK), a collection of...image processing kernels for applications such as diagnostic ultrasound and optical coherence tomography (OCT), where high computational performance at low power levels and clear image quality are important."

Recent news has been more meaningful on the Sitara front. As a reminder, TI first unveiled the Sitara brand name last October, in conjunction with announcing the latest members of a family of high-integration ARM Cortex-A8 SoCs which include a 2-D display engine and, in some product variants, an Imagination Technologies PowerVR SGX530 3-D graphics core. Even further integration in the form of a TMS320C674x DSP core creates the pin-compatible Integra product line. The family of six new Sitara devices introduced earlier this month is also Cortex-A8-based (Figure 1), suggesting that while this particular ARM CPU core variant may be fading away in applications such as smartphones and tablets, it has a long life ahead of it in the embedded market.

Figure 1. Texas Instruments' new six-member Sitara family offers an abundance of feature options.

Peer closely at the respective block diagrams, however, and you'll discover notable differentiation between last- and this-fall's Sitara offerings (Figure 2).

Figure 2. AM335x Sitara SoCs embed peripherals that target broader embedded usage than was the case with the multimedia-focused AM389x precursors.

First and foremost, the peak CPU clock speed this time around is 720 MHz (550 MHz for the 13x13 mm package option), half (or less) that of last year's devices. When I asked Texas Instruments for clarification, a spokesperson responded, "These new AM335x ARM MPUs are optimized for customer needs—the proper balance of high integration and performance with a low-power and low-cost." Admittedly, she's got a point; whereas the lowest-priced 2010 Sitara offering was $43 (quantity 1,000), TI is promoting these new ICs as low as $4.99 (quantity 10,000), attempting in the process to up-sell customers beyond ARM9-based product alternatives. And, whereas last fall's SoCs claimed 5-7 W active power consumption, TI specs these parts at as low as 7 mW (standby) and 700 mW (active) power. The fact that these chips leverage a 45 nm process, whereas the Sitara precursors are built on a 40 nm lithography, may also at least partially explain the clock speed disparity.

While the optional PowerVR 3-D graphics core remains, the 48 KBytes of boot ROM is absent from these new devices, as is the HD Video Processing Subsystem along with the corresponding Media Controller (and its 512 KBytes of RAM) and integrated HDMI transmitter. In their place, you'll find the following function blocks:

  • A security processor with cryptography acceleration and 64 KBytes of shared RAM
  • A 24-bit WXGA-resolution LCD controller with associated touchscreen controller, and
  • An optional PRU (programmable real-time unit) subsystem, containing two 200 MHz proprietary and limited-instruction-set 32-bit RISC cores. For those of you unfamiliar with their purpose, this slide set (PDF) explains that they are "specifically designed for manipulation of packed memory mapped data structures and implementing system features that have tight real time constraints", and conversely that they are "not a H/W accelerator to speed up algorithm computations" and more broadly "not a general purpose RISC processor."

The I/O port mix is somewhat different this time, too, reflective of a broader embedded focus, and including optional EtherCAT and Profibus support. Note that while Sitara devices don't contain the integrated DSP cores of their Integra counterparts, this exclusion doesn't preclude their usage in digital signal processing applications. For example, the PowerVR graphics core can also be used for beyond-graphics GPGPU applications in conjunction with an API such as OpenCL. Also, the Cortex-A8 supports the NEON SIMD floating-point instruction set.

The two high-end members of the AM335x Sitara family, the XAM3358ZCE and XAM3359ZCZ, are currently available for sampling and are scheduled to enter volume production in the second quarter of next year, along with the remainder of the announced product line. An evaluation module, the TMDXEVM3558, will be available for $995 beginning next month. For now, you can begin your development using the AM3358-based and $89 BeagleBone from BeagleBoard.org. A Linux-targeting EZ SDK, also including Android v2.2 support, will also be available for free download next month, with Windows Embedded Compact 7 support coming next quarter and QNX, Mentor and Wind River RTOS support available beginning later this quarter.

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