Comp.DSP FAQ: Part 3

Q3: Programmable DSP chips and their software

Q3.1: What are the available DSP chips and chip architectures?

Updated 05/07/02

The "big four" programmable DSP chip manufacturers are Texas Instruments, with the TMS320C2000, TMS320C5000, and TMS320C6000 series of chips; Freescale, with the DSP56300, DSP56800, and MSC8100 (StarCore) series; Agere Systems (formerly Lucent Technologies), with the DSP16000 series; and Analog Devices, with the ADSP-2100 and ADSP-21000 ("SHARC") series. A good overview of programmable DSP chips is published periodically in EDN and Computer Design magazines.

You may also want to check out Berkeley Design Technology's home page, which has a number of articles on choosing DSP processors, as well as a "Pocket Guide to Processors for DSP" in HTML format. Brief overviews of various DSP processors, cores, and general-purpose processors can be found at

Here's a less ambitious chip breakdown by manufacturer:

Agere Systems (formerly Lucent Technologies):

100 to 170 MHz 16-bit fixed-point DSP. The DSP16000 core features two multipliers with SIMD-like capabilities, a 20-bit address bus, a 32-bit address bus, and eight 40-bit accumulators. The chips feature two serial ports and two timers.

The first-generation processor, the DSP16210, contains a single DSP16000 core and 120 KB of internal RAM. The second-generation DSP16410 incorporates two DSP16000 cores and 386 KB of internal RAM.

Analog Devices:

10 to 80 MHz 16-bit fixed point DSPs; 40-bit accumulator; 24-bit instructions. Large number of family members with different configurations of on-chip memory and serial ports, timers, and host ports. ADSP-21mspxx members include an on-chip codec.
160 MHz 16-bit fixed point DSPs; 40-bit accumulator; 24-bit instructions. Based on the ADSP-21xx family, and is is mostly, but not completely, assembly source-code upward compatible with the ADSP-21xx Adds new addressing modes and an instruction cache, expands address space, and lengthens pipeline (six stages compared to three on the ADSP21xx). Family includes members containing multiple ADSP-219x cores.
ADSP-21xxx ("SHARC"):
33 to 100 MHz floating-point DSP; Supports 32-bit fixed-point, IEEE format 32-bit floating-point, and 40-bit floating-point; 40-bit registers plus an 80-bit accumulator that can be divided into two 32-bit registers and a 16-bit register.

The first-generation SHARC, the ADSP-2106x, features a single data path, a 32-bit address bus, and 40-bit data bus. Versions are available with up to 512 KB of on-chip memory, up to six communication ports, and up to 10 DMA channels.

The second-generation ADSP-2116x has two parallel data paths, a 32-bit address bus, and a 64-bit data bus. Versions are available with up to 512 KB of on-chip memory; up to six communication ports, and up to 14 DMA channels.

Analog Devices also sells the AD14000 series, which contain four ADSP-2106x SHARC processors in a single-chip package.
200 to 300 MHz 16-bit fixed point DSPs that can execute two MAC instructions per cycle; based on the ADI/Intel MSA core. Uses a mix of 16-, 32-, and 64-bit instructions. Features include ability to operate over a wide range of frequencies and voltages.


66 to 160 MHz 24-bit fixed-point DSP; most family members have 24-bit address and data busses. The DSP563xx also features 56-bit accumulators (2), timers, serial interface, host interface port. The DSP56307 and DSP56311 contain a filter co-processor. Up to 1 MB of internal RAM.
40 MHz 16-bit fixed point DSP; 36-bit accumulators (2), three internal address buses (two 16-bit, one 19-bit) and one 16-bit external address bus; three 16-bit internal data buses, one 16-bit external data bus; serial ports, timers. 4-12 KB of internal RAM. Most family members include an on-chip A/D.
160 MHz 16-bit fixed point DSP based on the DSP568xx. Adds an exponent detector and two accumulators, extends shifter and the logic unit to 32 bits, and widens internal address and data buses. The DSP5685x uses a 1X master clock rate rather than the 2X master clock rate used by the DSP568xx.
The 300 MHz MSC8101 is the first processor based on the StarCore SC140 core. It contains four parallel ALU units that can execute up to four MAC operations in a single clock cycle. The MSC8101 uses variable-length instructions. Features include: 512 KB on-chip RAM; 16 DMA channels; an on-chip filter co-processor; and interfaces for ATM, Ethernet, E1/T1 and E3/T3, and the PowerPC bus.

Texas Instruments:

20-40 MHz 16-bit fixed-point DSPs oriented toward low-cost control applications; 16 bit data, 32 bit registers. The family members have a variety of peripherals, such as A/D converters, 41 I/O pins, and 16 PWM outputs. A variety of RAM and ROM configurations are available

TI also sells the TMS320C2x family, an older version of the chip with fewer features.
33-75 MHz floating point DSPs; 32-bit floating-point, 24-bit fixed-point data, 40-bit registers; DMA controller; serial ports; some support for multi-processor arrays. Various ROM and RAM configurations.
40 to 160 MHz 16-bit fixed-point DSPs with a large number of specialized instructions. Many family members; the processors differ in configuration of on-chip ROM/RAM, serial ports, autobuffered serial ports, host ports, and time-division multiplexed ports. On-chip RAM ranges from 10 KB to over 1 MB.
144 to 200 MHz dual-ALU variant of the TMS320C54xx that can execute two MAC instructions per cycle. Variable instruction word width. Features include up to 320 KB internal RAM; 6 DMA channels; 2 serial ports; and 2 timers.
150-300 MHz 16-bit fixed-point DSP with VLIW (very large instruction word), load/store architecture; 32 32-bit registers; very deep pipeline; two multipliers, ALUs, and shifters; cache.
400-600 MHz 16-bit fixed-point DSP based on the TMS320C62xx. Adds SIMD support to most execution units, including extensive 8-bit SIMD support. Also doubles data bandwidth and increases size of on-chip memory.
100-167 MHz 32-bit and 64-bit IEEE-754 floating-point DSP with VLIW (very large instruction word), load/store architecture; 32 32-bit registers; very deep pipeline; two multipliers, ALUs, and shifters; cache.

Q3.2: What is the difference between a DSP and a microprocessor?

Updated 04/02/01

The essential difference between a DSP and a microprocessor is that a DSP processor has features designed to support high-performance, repetitive, numerically intensive tasks. In contrast, general-purpose processors or microcontrollers (GPPs/MCUs for short) are either not specialized for a specific kind of applications (in the case of general-purpose processors), or they are designed for control-oriented applications (in the case of microcontrollers). Features that accelerate performance in DSP applications include:

* Single-cycle multiply-accumulate capability; high-performance DSPs often have two multipliers that enable two multiply-accumulate operations per instruction cycle; some DSP have four or more multipliers
* Specialized addressing modes, for example, pre- and post-modification of address pointers, circular addressing, and bit-reversed addressing
* Most DSPs provide various configurations of on-chip memory and peripherals tailored for DSP applications. DSPs generally feature multiple-access memory architectures that enable DSPs to complete several accesses to memory in a single instruction cycle
* Specialized execution control. Usually, DSP processors provide a loop instruction that allows tight loops to be repeated without spending any instruction cycles for updating and testing the loop counter or for jumping back to the top of the loop
* DSP processors are known for their irregular instruction sets, which generally allow several operations to be encoded in a single instruction. For example, a processor that uses 32-bit instructions may encode two additions, two multiplications, and four 16-bit data moves into a single instruction. In general, DSP processor instruction sets allow a data move to be performed in parallel with an arithmetic operation. GPPs/MCUs, in contrast, usually specify a single operation per instruction

While the above differences traditionally distinguish DSPs from GPPs/MCUs, in practice it is not important what kind of processor you choose. What is really important is to choose the processor that is best suited for your application; if a GPP/MCU is better suited for your DSP application than a DSP processor, the processor of choice is the GPP/MCU. It is also worth noting that the difference between DSPs and GPPs/MCUs is fading: many GPPs/MCUs now include DSP features, and DSPs are increasingly adding microcontroller features.

Q3.3: Software for Analog Devices DSPs

Updated 12/01/2006

Q3.3.1: Where can I get a C compiler for the ADSP-21xx and ADSP-21xxx?

The G21 package collects the free source code for the Analog Devices GCC-based C compilers for their 21xxx (SHARC) and 21xx series DSPs. These compilers are all based on GCC version 2.3.3. Full source code for the compiler, assembler, linker, etc. is available at

The C compilers are available for the 210x series as well as for the SHARC. The assemblers and linkers are only available for the SHARC. The source code is based on what is released under GPL by ADI, but is adapted for use with Linux and other Unix variants.

[Egil Kvaleberg,]

Q3.3.2: Where can I get tools for the ADSP-21xxx?

SHARC development tools are avaiable for Acorn/BSD, Linux, and other platforms. The tools include frontend/preprocessor , assembler, linker, archiver, a utility to generate ROM images for eprom burners, and other utilities The supplied assembler is not part of the gnu archive, but is based on a assembler originaly written by P. Lantto. Source code and binaries are available at:

Q3.3.3: Where can I get algorithms or libraries for Analog Devices DSPs?

The number for the Analog Devices DSP BBS is (617) 461-4258 (300, 1200, 2400, 9600, 14400 bps), 8N1.

You can also find files on Analog Devices' web site at, or at their FTP site at

[Analog Devices DSP Applications,]

Q3.4: Software for Agere Systems (Formerly Lucent Technologies) DSPs

Agere Systems provides application libraries for their DSPs at

Q3.5: Software for Freescale DSPs

Updated 12/01/2006

Freescale provides free software development tools that may be downloaded from the Freescale Web site at

Q3.5.1: Where can I get a free assembler for the Freescale DSP56000?

A free assembler for the Freescale DSP56000 exists, thanks to Quinn Jensen, The current version is 1.2. It is also available at

Q3.5.2: Where can I get a free C compiler for the Freescale DSP56000?

There are two separate compiler sources for the Freescale DSP56000. One is the port of gcc 1.40 done by Andrew Sterian ( and the other is a port of gcc 1.37.1 done by Freescale and returned to the FSF. Andrew's port has bowed to Freescale's version. Both may be portable to gcc2.x.x with some effort required. Neither of these comes with an assembler, but you can get a free DSP56000 assembler elsewhere (see question 3.5.1, above). The Freescale gcc source is available for FTP from:

From Andrew Sterian, "My DSP56K compiler, while not supported nor as well tested as Freescale's, implements fixed-point arithmetic rather than floating-point arithmetic. This may be suitable for some applications. The 5615 compiler also implements fixed-point arithmetic. To the best of my knowledge, Freescale does not have a C compiler for the 5615 family, although alternatives may exist. As of this writing (January 1997) I have not worked with Freescale DSPs or compiler software for nearly 5 years so questions regarding my compilers may well be met with "Ummm... I have no idea."

Both compilers were posted to alt.sources so any Usenet site that archives this newsgroup will have a copy. I have also found the 5616 compiler at ( IsoPod(TM) - based on the DSP56F805. The assembler generates output suitable for Freescale's free JTAG flash loader.

Pete Gray has announced the availability of a Small C cross-compiler (with source) and assembler for the Freescale DSP56800, available for download from . Targetting a simple DOS-box host, developed and tested using djgpp ( and Metrowerks CodeWarrior, in conjunction with NMI's ( IsoPod(TM) - based on the DSP56F805. The assembler generates output suitable for Freescale's free JTAG flash loader.

Small C language reference available online at

Q3.5.3 Where can I get a disassembler for the Freescale DSP56000?

Miloslaw Smyk has released an open source (BSD style) 5600x disassembly library. It is available for download at [Miloslaw Smyk,]

Q3.5.4: Where can I get algorithms and libraries for Freescale DSPs?

Freescale provides a software archive that is available via World-Wide Web from the software page at The archive includes macros for filters (FIR, IIR, adaptive) and floating-point functions. [Tim Baggett]

Q3.5.5: Where can I get NeXT-compatible Freescale DSP56001 code?

Try FTP at The /pub/ directory contains free code for the Freescale DSP56001 and the NeXT platform. [bil@ccrma.Stanford.EDU]

Q3.5.6: Where can I get emulators for the 68HC11 (6811) processor?

While the 68HC11 is not a DSP processor, emulators are available for those who might be interested in doing DSP on these processors:

* New Mexico State University (NMSU) simulator engine, (Unix). Simulator engine with a command-line interface.
* Sim6811, (Mac). Screen-oriented user interface based on the NMSU simulator engine (plus bug fixes).
* THRSim11, allows you to edit, assemble, simulate and debug programs for the 68HC11 on Windows 95/98. THRSim11 simulates the CPU, ROM, RAM, all memory mapped I/O ports, and the on board peripherals.

Q3.6: Software for Texas Instruments DSPs

Updated 12/01/2006

Q3.6.1: Where can I get free algorithms or libraries for TI DSPs? has some old, apparently public domain, assembler and related tools from TI for the TMS320 family.

TI has a number of free algorithms available on their website at

TI's world-wide web site is The TI DSP bulletin board is mirrored on The TI site is the official one, but has no user contributed software. [Brad Hards,]

{ If anyone knows of any other sources for TI DSP software, please let us know at Thanks! }

Q3.6.2: Where can I get free development tools for TI DSPs?

TI development tools are available for free 30 day evaluation on the TI website.
Go to

Q3.6.3: Where can I get a free C compiler for the TI TMS320C3x/4x?

The GNU binutils 2.11 and later have been ported to the TI C54xx/IBM C54DSP. Most of the binutils tools are supported, including the assembler, linker and objdump. The assembler is source-compatible with the TI assembler. The GNU binutils are available from GDB ports for c25/c5x/c54x are also available.

[Timothy Wall]

Dr. Michael P. Hayes has written a GNU C-based compiler for the TMS320C30 and TMS320C40 families, available at The current version patches against gcc-2.8.1; support is moving to egcs-1.2. The compiler is freely redistributable under the terms of the GNU Public License. Front-ends are also available for C++, Java, Fortran 77, Pascal, Ada 95, among others.

[Dr. Michael P. Hayes,]

Q3.6.4: Where can I get a free assembler for the TI TMS320C3x/4x?

Ted Rossin has written an assembler and linker for the TMS320C30. In his words, "It is somewhat limited by the fact that it can't handle expressions but it has worked fine for me over the past few years. There is no manual because it is a clone of the TI assembler and linker. However the linker command files use a different (easier to use) syntax. It runs on HP-UX workstations, Macs, IBM clones and believe it or not the Atari-ST (because I developed the code on it)."

[Ted Rossin,]

Dr. Michael P. Hayes has written a GNU-based assembler for the TMS320C30 and TMS320C40 families, available at The current version patches against binutils-2.7. According to Michael Hayes, the assembler syntax is compatible with the Texas Instruments TMS320C30 assembler, although not all the Texas Instruments directives are supported. The binutils include a linker (ld), archiver (ar), disassembler (objdump), and other miscellaneous utilities. The object format of the assembler is compatible with the COFF format used by the Texas Instruments assembler. The assembler and other binary utilities are freely redistributable under the terms of the GNU Public License.

[Dr. Michael P. Hayes,]

Q3.6.5: Where can I get a free simulator for the TI TMS320C3x/4x?

A freely distributable instruction set architecture simulator is available for the TMS320C30 DSP as part of the Web-Enabled Simulation framework from UT Austin at

We have released all of the source code, as well as prebuilt C30 simulators for Windows '95/NT and Solaris 2.5 architectures.

The C30 simulator is bit-, cycle-, and instruction-accurate. The behavior of the C30 simulator has been validated against a C30 DSK board. The C30 simulator correctly reports interlocking and pipeline flushes, so it provides a convenient way to check C30 programs for these hidden delays. The C30 simulator is based on the C30 DSK tools by Keith Larson at Texas Instruments.

[Brian Evans,]

Herman Ten Brugge ( has also written a GNU debugger (GDB) based simulator for the TMS320C30 and TMS320C40, available via anonymous FTP at This is freely redistributable under the terms of the GNU Public License.

This simulator allows you to debug your programs without having to a connect to a real C[34]x target system. It will also profile your code showing you where the pipeline conflicts are occurring. You can connect I/O ports to files (or TCP/IP sockets), trigger interrupts, examine the cache etc. It will detect different threads of control running and generate a profile summary for each thread, annotating both the C code and assembler code with the number of executed cycles.

[Dr. Michael P. Hayes,]

Q3.6.6: What is Tick? Where can I get it?

Tick is a TMS320C40 parallel network detection and loader utility.

It is available from:

Supports: Transtech, Hunt, and Traquair boards hosted by DOS, SunOS, Linux