At last month’s Embedded Processor Forum, ARC described extensions to its ARCtangent customizable processor core that target VoIP applications. The extensions include enhanced saturation and rounding support for existing ALU, shifter, and multiplier operations, and new operations like absolute value and negate. These instructions are intended to improve performance on applications that conform to the bit-exact ITU and ETSI specifications for voice compression algorithms such as G.729.

Customizable processors were all the rage at this year’s Embedded Processor Forum. Vendors from Tensilica to Toshiba touted customizable processors as the ultimate solution for DSP applications from voice-over-IP to MPEG-4 video compression. In the view of these companies, processors with fixed instruction sets are forever bound to be jacks-of-all-trades, but masters of none. A better approach, they argue, is a flexible instruction set that designers can fine-tune to do one thing well.

In February Analog Devices announced that the 250 MHz TigerSHARC had at long last reached full production. Analog Devices says this processor is particularly suitable for 3G cellular base stations; TigerSHARC also targets high-performance fixed- and floating-point defense, medical, and video applications.

A battle of the titans is shaping up for supremacy in embedded application processors—processors intended for next-generation portable information appliances like multimedia cell phones and PDAs. The stakes in this battle are enormous: according to Micrologic Research, worldwide cell phone shipments alone are expected to exceed 450 million units this year. And the contestants are appropriately gargantuan: Texas Instruments, the long-time king of digital signal processors (DSPs), is pitted against Intel, the 800-pound gorilla of general-purpose processors (GPPs).

On Friday, April 5, DSP Group and Parthus announced the merger of DSP Group's IP licensing business with Parthus, forming a new company, ParthusCeva, Inc. According to the companies, ParthusCeva will be "the leading independent provider of DSP-based IP solutions." Many observers view the deal as another step in the inevitable consolidation of the silicon IP business, as a large number of competitors face a skittish market and seek ways to strengthen their positions.

In the early days of the automotive industry, every car was a unique, handcrafted specimen—even mundane items like pistons were one-of-a-kind. This changed in 1908, when Cadillac disassembled three Model K's, mixed the parts together, and then built three running cars from the hodgepodge of parts. Today, this feat seems wholly unremarkable—even cars as seemingly dissimilar as Fords and Jaguars often share major components. One of the great lessons of the 20th-century automotive industry is that differences between vehicles should exist only where they add value.

On February 11, Altera introduced its all-new Stratix family of FPGAs. These FPGAs feature hard-wired DSP logic blocks; each DSP block can perform up to eight 9-bit, four 18-bit, or one 36-bit multiplications per cycle, with optional accumulation of up to two results. The DSP blocks also contain "pipeline registers;" using these registers increases latency but allows the DSP block to operate at higher clock rates--at over 250 MHz, according to Altera.