On February 11, Altera introduced its all-new Stratix family of FPGAs. These FPGAs feature hard-wired DSP logic blocks; each DSP block can perform up to eight 9-bit, four 18-bit, or one 36-bit multiplications per cycle, with optional accumulation of up to two results. The DSP blocks also contain "pipeline registers;" using these registers increases latency but allows the DSP block to operate at higher clock rates--at over 250 MHz, according to Altera.
The main competitor for the Stratix family is the Xilinx Virtex-II family of FPGAs already in production. Both product lines feature hard-wired multipliers, optional Simulink-based DSP development tools, on-chip terminating resistors, and support for numerous high-speed I/O protocols. In contrast to the selectable data width and optional pipelining and accumulation of the Stratix DSP blocks, the Virtex-II family contains fixed-function 18-bit multipliers with no hard-wired accumulators. Announced Virtex-II devices contain up to 168 18-bit multipliers; announced Stratix devices contain up to 112 18-bit multipliers.
Echoing the differences in the hard-wired multipliers, the two families take differing approaches to on-chip memory; the Virtex-II family provides uniform memory resources, while the Stratix family provides varied and somewhat more complex memory resources. Virtex-II devices contain 18 Kbit blocks of RAM, and each logic cell can alternatively function as 16 bits of memory. In contrast, Stratix devices contain 512 bit, 4 Kbit, and 512 Kbit blocks of RAM, but logic cells are not intended for use as memory.
The first Stratix device, the EP1S25, is expected to begin sampling in the second quarter of 2002, with full production expected in 2003. The EP1S25 contains 25,660 "logic elements," 1.85 Mbits of RAM, and 10 DSP blocks, and will be priced starting at $125 for high-volume orders.
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