Xilinx Buys AutoESL, Securing High-Level Synthesis Capabilities

Submitted by BDTI on Mon, 02/28/2011 - 21:00

Xilinx has acquired high-level synthesis start-up AutoESL Design Technologies, bringing the AutoPilot high-level-synthesis tool in-house. AutoPilot accepts a C, C++, or SystemC description of the functionality of an algorithm or task and generates a register-transfer-level (RTL) implementation in Verilog or VHDL.  The RTL implementation is then processed through the traditional FPGA RTL logic synthesis, place-and-route, and verification tool flow. Like other high-level synthesis tools, AutoPilot offers time savings in the RTL design and coding process, and speeds the verification process by enabling much of the verification work to be done at the C, C++, or SystemC level, where simulations are dramatically faster than those at the register or gate level.

High-level synthesis tools have been around for decades, but have not been widely adopted for several reasons, including the quality of results produced and cost of the tools.  AutoPilot, however, has been shown to deliver DSP-centric FPGA designs with chip resource utilization comparable to hand-coded RTL design.  BDTI performed an independent evaluation of AutoPilot in 2009 as part of the BDTI High-Level Synthesis Tool Certification Program. In February 2010, BDTI published the results of the study in the paper, “An Independent Evaluation of the AutoESL AutoPilot High-Level Synthesis Tool.”

BDTI’s methodology for its high-level certification program relies on two well-defined sample applications, or “workloads,” that provide a quantitative comparison of quality of results for different design flows and chip targets. A video-processing application is used to compare an FPGA realization generated via high-level synthesis with an optimized software implementation hosted on a DSP. A DQPSK receiver application is used to compare the quality of RTL code delivered from a high-level synthesis tool with hand-coded RTL–both targeting the same FPGA.

The receiver workload evaluation showed equal quality of results for AutoPilot- and hand-generated RTL designs. The video workload tests reaffirmed the performance advantage that BDTI has previously found for FPGAs over DSPs in some applications:  The parallel structure of an FPGA can offer 40x better performance than a DSP in parallelizable, data-flow-intensive algorithms such as the video workload.  (View the paper for details.)

A less obvious benefit of high-level synthesis is that rapid generation of RTL implementations can enable designers to experiment with design trade-offs (for example, trading off processing latency against performance) to a greater degree than would be practical with hand-written RTL design, increasing the likelihood of finding a near-optimal design point.

As high-level synthesis tools such as AutoPilot have improved the quality of results that they generate, the price of these tools has remained an obstacle to their widespread use.  High-level synthesis tools typically sell for $50,000-100,000 per seat.  Traditional RTL FPGA design tools, in contrast, are generally much less expensive or even free. Xilinx has not announced pricing plans, but we expect the company to offer AutoPilot at a much lower price point than has previously been typical for such tools.

In addition to gaining discretion over its selling price, by buying AutoPilot Xilinx also ensures that the tool remains available to Xilinx customers—and not to users of competing FPGAs.  According to Xilinx, the company will honor existing contractual agreements to support customers using other targets–including competing FPGAs or ASICs. In the medium term, though, we expect AutoPilot to support only Xilinx FPGAs.

Perhaps the most interesting question about the Xilinx acquisition of AutoESL is how Xilinx will use AutoPilot with its forthcoming Extensible Processing Platform (EPP), which will combine a high-performance ARM CPU subsystem and an FPGA fabric.  Some articles on the acquisition suggest that a system designer will be able to use a single code base that can be flexibly partitioned between the CPU and the FPGA fabric.  This is an appealing idea, but we believe there’s much work to be done before this vision is realized.  Today, designers must optimize their high-level language code with the target CPU or FPGA architecture in mind in order to achieve efficient implementations.

Leaving speculation about future design methodologies aside, it’s clear that AutoPilot can accelerate key steps of the FPGA design process for an important class of designs.  Through better integration with Xilinx’s RTL design tools, and more accessible price point, Xilinx has the potential to both grow its customer base—by enabling system, algorithm, and software designers to get more involved in FPGA design—and to boost the productivity of its current customers.

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