Synfora’s PICO High-Level Synthesis Tool Achieves BDTI Certification

Submitted by BDTI on Thu, 03/18/2010 - 19:00

BDTI recently completed an in-depth evaluation of Synfora’s PICO tool through the BDTI High-Level Synthesis Tool Certification Program™.  BDTI evaluated the process of implementing applications on a Xilinx FPGA using PICO, comparing it with traditional FPGA design based on hand-written RTL code, and with DSP processor software development.  PICO enabled creation of efficient FPGA implementations, with design productivity comparable to that of DSP processor software development.  The algorithmic C code required fewer modifications than the code that was used to implement the design on a DSP processor, while providing over a 30X improvement in price/performance.

The original PICO technology was developed by HP Labs, and was licensed to Synfora in 2003.  (“PICO” is an acronym for “program in, chip out.”)  Synfora’s PICO tool accepts C or C++ code (restricted to specified subset of these languages), and compiles it to a hardware implementation in the form of RTL code for FPGA or ASIC implementation. 

BDTI used a video application for this evaluation.  A BDTI DSP engineer with significant software development and optimization experience, but without RTL design experience, used PICO to generate an FPGA implementation in the form of RTL code.  An experienced FPGA engineer then shepherded this RTL code (without modification) through the Xilinx logic synthesis and placement-and-routing tools, and integrated it with I/O interfaces, to finalize the FPGA implementation.

Synfora provides strong documentation and extensive classroom training to assist users in learning to use PICO.  Initially, the BDTI DSP engineer completed a half-day online tutorial, followed by two days of classroom training. Synfora’s training and documentation provided an appropriate introduction to general hardware implementation considerations as well as PICO-specific implementation techniques.   Later in the design process the engineer completed an additional day of advanced training primarily focused on optimization for clock speed and resource usage.

For BDTI’s example video application, algorithmic C reference code was provided as a starting point.  As a first step in building the application using PICO, the BDTI engineer modified the C code to comply with PICO’s restrictions.  The most significant restrictions include lack of support for printf() statements, pointers, dynamic memory allocation (i.e., malloc), and static variable assignments.  These initial code modifications took approximately one day.  During this process, unsupported language constructs were identified via PICO error messages. 

Once the code was made PICO-ready, it took PICO about 20 minutes to generate the initial FPGA implementation RTL code, including generation of detailed reports on the FPGA resource requirements for each module of the design.  (While 20 minutes isn’t an unreasonable amount of tool run time for such a complex task, faster run times would be valuable, enabling the engineer to try more options more quickly.)  The resource reports showed that the synthesized design required too much on-chip memory—an expected result given the frame-oriented nature of the reference C code.  The BDTI engineer modified the code to transfer data from one function to another on a pixel-by-pixel basis using minimal buffering within the design.  He then specified bit width constraints using pragmas (tool-directed comments embedded in the code) to minimize logic requirements.

After the completion of these steps, PICO reported that the design would fit in the target FPGA, but that it would not meet the clock speed requirements of the application.  In order to resolve the clock speed issue, the BDTI engineer restructured the C code to make hardware inferences easier for the tool.  This restructuring is required in part because PICO performs dependence analysis only for loops which are coded using a limited subset of C or C++ constructs.  For example, the tool could not infer optimal hardware from certain C constructs, such as a for loop inside of an if statement, and for loops with certain types of increment variables or exit conditions.

The BDTI engineer then performed additional optimizations on the C code to improve resource utilization.  For example, this included replacing a multiply-by-negative-eight operation with code specifying a shift-and-invert operation, and minimizing FPGA memory by packing data into structures in such a way as to make memory re-use potential more visible to the tool.  After resolving these issues, PICO generated an implementation that fit on the target FPGA and achieved the required clock speed. 

Throughout the design process PICO’s strong visualization and analysis capabilities were very helpful, including mapping C to RTL code with source-level linking, graphs showing the inference of sequential and parallel blocks of code, and memory utilization histograms which helped to minimize buffering requirements. 

Many PICO capabilities were not tested in BDTI’s certification program, including the ability to generate models for system-level and timing-accurate simulation. Synfora also reports that its customers have used PICO successfully in much larger designs (for example, a design occupying 70% of a Xilinx Virtex-5 device) than those used in BDTI’s certification program.

In summary, the BDTI certification results show that PICO can produce efficient FPGA designs, with resource use comparable to hand-written RTL code.  PICO’s C-based design flow offers good productivity and ease of use compared to a traditional hand-coded RTL design.

Full evaluation results and a description of BDTI’s methodology are available on the BDTI web site. 

Add new comment

Log in or register to post comments