Synphony Synthesis Tool Takes MATLAB to RTL

Submitted by BDTI on Wed, 10/21/2009 - 18:00

High-level synthesis tools (i.e., tools that take high-level language code and generate an RTL-based hardware implementation) have been around a long time, but historically they have had limited success in the market. The primary problems have been that they have been hard to use and have generated relatively inefficient implementations.  But their potential advantages are compelling, particularly as applications become more complicated: in the best case they can reduce implementation time and errors, and possibly reduce the need for RTL experts.  For these reasons, a number of vendors have introduced high-level synthesis tools in recent years, including AccelChip (later acquired by Xilinx), Mentor Graphics, Cadence, AutoESL, and Synfora, among others. Most of these take C representations as inputs and synthesize them into RTL for FPGA or ASIC implementation, though some have promised MATLAB to RTL. 

This month, Synopsys announced a new high-level synthesis tool, “Synphony,” that   takes input MATLAB M files and synthesizes them directly into RTL hardware implementations. Interestingly, Synphony does not support C to RTL synthesis; the tool is designed exclusively for designs expressed in the M language. Synopsys says that the tool is designed for applications that rely heavily on algorithm development, such as wireless and wired communications and multimedia.  The tool is intended to take an algorithm developed in MATLAB and generate RTL for implementation on an FPGA or ASIC. According to Synopsys, Synphony supports a subset of the M language that includes most of the constructs that would be applicable to hardware design.

In addition to generating RTL output, Synphony generates C models of the input algorithm for verification purposes. According to Synopsys, simulation using the C models is a hundred times faster than RTL simulation. Synphony does not incorporate timing estimation.  For ASIC designs, timing estimation is accomplished using Synopsys’ Design Compiler tool; for FPGA designs users can use Synopsys’ Synplify Pro/Premier tool.

Synphony supports semi-automatic conversion from floating-point to fixed-point math. Floating-point data is commonly used during algorithm development because it provides more dynamic range and easier algorithm verification, while production implementations typically use fixed-point math because it requires less power and fewer gates.  In general, the process of converting from floating-point to fixed-point math is non-trivial and requires careful analysis of the algorithm; it’s not particularly well suited to push-button conversion. Synphony’s float-to-fixed conversion feature is intended to reduce the time required and errors associated with the conversion process. According to Synopsys, the process is not entirely automatic, and the user has to provide some guidance to the tool.

A key question for synthesis tools is how efficient the resulting RTL implementation is, relative to hand-coded RTL. According to Synopsys, Synphony optimizes the generated RTL using a number of techniques, including automatic loop unrolling, scheduling, pipelining, and target-specific optimizations for FPGAs and ASICs. Synopsys has not released any quantitative comparisons of the quality of results of Synphony-generated RTL compared to hand-coded RTL; this will no doubt prove to be critical to the tool’s success. 

Synphony is in beta release now, and is expected to be generally available in December 2009.

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