At the end of March, Xilinx announced availability of the first two members of its Virtex-5 FXT platform, the FX30T and FX70T. The Virtex-5 FXT platform is geared towards serial communications and embedded applications, and joins three other Virtex-5 platforms: the LX, which is intended for logic-intensive applications; the LXT, which targets logic and serial communications; and the SXT, which is intended for serial communications and DSP. (The “T” in the platform name indicates that the chips contain transceivers.) Target applications for the new FXT chips include video-over-IP, wireless base stations, and other high-performance applications.
Xilinx announced the four Virtex-5 platforms back in 2006, along with availability of Virtex-5 LX chips. (The company had originally planned to have all four platforms shipping by mid-2007, but the FXT chips have slipped out a bit.) Xilinx’s strategy with the four platforms is to enable designs optimized on one platform to be easily ported to another. Following the FX30T and FX70T, three more FXT chip variants (the FX100T, FX130T, and FX200T) are expected to become available in the next six months. Pricing for the initial FXT chips starts at $159 in 1K volumes (projected for the second half of 2009).
The new FXT chips include embedded PowerPC 440 processors (up to two) and lots of high-speed serial transceivers (from 8 to 24). These aren’t the first PowerPC-equipped Virtex chips—Xilinx also embedded PowerPCs in its previous-generation Virtex-4—but this is their first appearance in the Virtex-5. The PowerPCs in the 65 nm Virtex-5 FXT chips are a bit faster than those in the 90 nm Virtex-4; they operate at up to 550 MHz compared to 450 MHz. (Xilinx also offers a 32-bit RISC soft processor core, MicroBlaze, that can be implemented in the FPGA fabric.)
Like the other Virtex-5 platforms, the FXT chips incorporate hardwired DSP logic blocks, called “DSP48e slices.” Each slice includes a 25×18-bit multiplier, an adder, and multiplexers to support fast multiply-accumulates (MACs) and other DSP-oriented processing. These slices are somewhat different than the DSP slices used in the Virtex-4; for example, the older slices used 18×18-bit multipliers rather than 25×18-bit. Xilinx says that the move to 25×18-bit multipliers enables them to perform FIR filtering with greater dynamic range and fewer FPGA resources, and to implement single-precision floating-point adds and multiplies using half the FPGA resources required by the 18×18-bit version. FXT chips include 64 to 384 DSP48e slices, which can be clocked at up to 500 MHz.
Using the PowerPC, DSP slices, and transceivers, Xilinx envisions that the new chips will be able to eliminate the need for a separate processor and DSP hardware in many applications, thus implementing more of the application and potentially reducing chip count and system cost, as shown below.
Figure 1. Virtex-5 FXT chips. (Table courtesy of Xilinx)
The FXT family is not the only new product announcement from Xilinx. In mid-May, Xilinx announced another high-performance Virtex-5 chip, this one from the SXT platform. As mentioned earlier, the SXT platform targets DSP-intensive applications, and has the maximum number of DSP48e slices of the four Virtex-5 platforms. The new SX240T is also aimed at high-performance computing (HPC) applications, and is by far the largest of the SXT chips, with roughly double the logic capacity of the next-largest device (the SX95T). The new SX240T chip also includes a whopping 1056 25×18-bit DSP48e slices (again, roughly twice that of the SX95T), along with 24 high-speed serial transceivers and 18 Mbits of RAM.
As we wrote in our 2007 report “FPGAs for DSP,” the number of multipliers and parallel resources in high-performance DSP-enhanced FPGAs is orders of magnitude higher than that available in high-performance DSP processors. These chips tend to be significantly faster and more cost-effective than DSP processors in some highly parallel applications—though these advantages come at the cost of much longer development cycles. We expect these characteristics to be true for the new SXT chip as well, though the chips’ pricing has not yet been announced.
As part of the SX240T announcement, Xilinx also introduced version 4.0 of its “floating-point operator” (FPO) IP core. The new core has been optimized to use the 25×18-bit multipliers and, according to Xilinx, it enables the SX240T to provide 190 GFLOPS of single-precision floating-point horsepower. The chips’ floating-point capabilities are important in many of the HPC applications it targets.
The SX240T is expected to begin sampling in the third quarter of 2008, with full production by the end of the year.
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