In the last month, FPGA vendors launched a wave of architectures targeting signal processing. These new architectures—the Xilinx Virtex-4, the Lattice Semiconductor LatticeECP, and the Altera Cyclone II—differ in many important respects, but all three feature hard-wired multipliers sprinkled among their reconfigurable logic elements.
Xilinx's new offering, the Virtex-4, targets high-performance applications. The Virtex-4 family contains three distinct sub-families that Xilinx calls "platforms." All three platforms use the same basic architecture, and all three offer hardwired multipliers. However, the platforms offer differing ratios of reconfigurable logic, multipliers, and other features. The LX "logic platform" emphasizes logic, while the SX "signal-processing platform" provides a larger number of hard-wired multipliers. The FX "full-featured platform"—which includes hardwired PowerPC cores and high-speed I/O—falls between the LX and SX platforms in terms of its logic-to-multipliers ratio.
Xilinx's current high-performance offering, the Virtex-II Pro, also contains hardwired multipliers. However, Virtex-4 includes several advances that make it better suited for signal processing applications. For example, Virtex-II Pro uses simple 18x18 multipliers that cannot perform accumulation or other non-multiplication operations. Virtex-4 uses more sophisticated hardware that can perform about thirty operations, including multiply-accumulate, shift, and normalize. In general, dedicated hardware is less expensive, more energy-efficient, and faster than reconfigurable logic. Because Virtex-4 moves operations such as accumulation into dedicated hardware, it should have significant advantages over the Virtex-II Pro in signal-processing applications that make heavy use of these operations.
The new Altera and Lattice architectures target low-cost applications. Despite targeting low-cost applications, the LatticeECP-DSP multiplier hardware is even more complex and powerful than that of the Virtex-4. The multipliers in the LatticeECP-DSP are organized in blocks; each block can perform one 36x36 multiplication, four 18x18 multiplications, or eight 9x9 multiplications. Each block can combine multiplication results using addition or subtraction, and then feed the results to built-in accumulator registers. Interestingly, the LatticeECP-DSP multiplier blocks are very similar to the multiplier blocks on Altera's high-performance Stratix II family.
In contrast to the approaches taken in the Virtex-4 and LatticeECP-DSP—and in Altera's own Stratix II—the Altera Cyclone II uses simple multipliers similar to those found on the Xilinx Virtex-II Pro. Each Cyclone II multiplier can perform either a single 18x18 multiply or two 9x9 multiplies, but there is no dedicated hardware for accumulation or other operations. Altera chose to use this simple, small multiplier hardware because Cyclone II is designed for minimum cost, not for maximum performance. Still, Cyclone II should offer much better signal-processing performance than the original Cyclone family, which does not contain any hardware multipliers.
Of course, multipliers alone do not determine an FPGA's suitability for signal-processing applications. However, it is encouraging to see that FPGA vendors recognize the growing importance of signal processing in both high-performance and low-cost applications.
The Xilinx Virtex-4 is expected to begin sampling this summer; Xilinx has not announced pricing for this family. The first Lattice Semiconductor LatticeECP-DSP devices are sampling now. The first part to begin sampling, the ECP-DSP20, will be priced at $59 in 1,000-unit quantities. The first Altera Cyclone II device is expected to begin sampling in February 2005. Altera has announced pricing for two mid-range parts, the EP2C20 and EP2C235. These devices will be priced at $49 and $89, respectively, in 1,000-unit quantities.
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