Observations From ISPC/GSPx

Submitted by BDTI on Thu, 05/15/2003 - 19:00

Last month BDTI participated in the International Signal Processing Conference and Global Signal Processing Expo (ISPC/GSPx) held in Dallas, Texas. The conference included many insightful presentations on tough signal-processing problems. The presenters represented a mix of corporations and universities, and topics ranged from practical tips to esoteric algorithms.

One of the more interesting presentations introduced AccelFGPA, a tool under development by the venture-backed start-up AccelChip. AccelFGPA uses techniques developed at Northwestern University to map algorithms described in MATLAB into FPGA implementations. This tool targets a fundamental problem of FPGA-based signal processing: few DSP application developers are familiar with the established design flows for FPGAs. In contrast, most DSP application developers are familiar with MATLAB, and DSP application designs often begin life as MATLAB models. A tool that translates MATLAB models to efficient FPGA implementations could be immensely useful. It will be interesting to see if AccelFGPA can deliver on this intriguing concept.

STMicroelectronics presented another interesting concept in its “OptiPAX” coprocessor architecture. The key feature of the OptiPAX architecture is its split-instruction transaction model. Typically, CPU cores send data to and request results from a coprocessor using a single instruction. As a result, the CPU may stall for several cycles while the coprocessor processes the data. In contrast, the OptiPAX architecture uses separate instructions to send data and to request results, allowing the CPU to access a coprocessor without stalling, even when the coprocessor operation requires multiple cycles. STMicroelectronics claims this subtle improvement can lead to large performance gains.

Other presentations shared practical insights into common signal-processing challenges. In one such presentation, Dror Halahmi of Motorola analyzed the impact of the MSC8102 cache system on the processor’s signal-processing performance and explained how some unusual features of the MSC8102 cache system can be used to mitigate this impact. It was encouraging to see a DSP vendor giving such close attention to this crucial but often-overlooked topic.

The quality of these presentations suggests that ISPC/GSPx is off to a good start. We look forward to participating in ISPC/GSPx again next year.

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