InsideDSP — In-depth analysis and opinion

Intrinsity Unveils 2 GHz Matrix Processor

At last month’s Embedded Processor Forum, Intrinsity revealed details of its MIPS32-based FastMIPS and FastMATH processors, the first processors to use Intrinsity’s “Fast14” dynamic logic technology. According to Intrinsity, Fast14 uses several novel techniques to avoid common dynamic logic problems like susceptibility to noise. Intrinsity claims Fast14 is up to three times faster than conventional static logic and backed up this claim by demonstrating a 2.2 GHz Fast14-based test chip last Read more...

ARC Addresses VoIP Applications

At last month’s Embedded Processor Forum, ARC described extensions to its ARCtangent customizable processor core that target VoIP applications. The extensions include enhanced saturation and rounding support for existing ALU, shifter, and multiplier operations, and new operations like absolute value and negate. These instructions are intended to improve performance on applications that conform to the bit-exact ITU and ETSI specifications for voice compression algorithms such as G.729. Read more...

Jeff Bier’s Impulse Response—Jack-of-All-Trades

Customizable processors were all the rage at this year’s Embedded Processor Forum. Vendors from Tensilica to Toshiba touted customizable processors as the ultimate solution for DSP applications from voice-over-IP to MPEG-4 video compression. In the view of these companies, processors with fixed instruction sets are forever bound to be jacks-of-all-trades, but masters of none. A better approach, they argue, is a flexible instruction set that designers can fine-tune to do one thing well. Read more...

DSP Software Library Supports x86, XScale

In April Intel announced version 2.0 of its Integrated Performance Primitives (IPP) library of DSP functions. This library is unusual in that it supports a diverse set of processor architectures: Itanium (IA-64), Pentium 4 and Xeon (IA-32), XScale, and StrongARM. Intel claims IPP 2.0 is highly optimized for each architecture, allowing application software developers to gain the benefits of hand-optimized code without delving into architecture-specific features. IPP 2.0 uses the same function Read more...

Jeff Bier’s Impulse Response—1600 lbs. of Gorilla

A battle of the titans is shaping up for supremacy in embedded application processors—processors intended for next-generation portable information appliances like multimedia cell phones and PDAs. The stakes in this battle are enormous: according to Micrologic Research, worldwide cell phone shipments alone are expected to exceed 450 million units this year. And the contestants are appropriately gargantuan: Texas Instruments, the long-time king of digital signal processors (DSPs), is pitted Read more...

DSP Group and Parthus Consolidate IP Businesses

On Friday, April 5, DSP Group and Parthus announced the merger of DSP Group's IP licensing business with Parthus, forming a new company, ParthusCeva, Inc. According to the companies, ParthusCeva will be "the leading independent provider of DSP-based IP solutions." Many observers view the deal as another step in the inevitable consolidation of the silicon IP business, as a large number of competitors face a skittish market and seek ways to strengthen their positions. DSP Group has been the Read more...

‘C64xx Family Gets Baby Brother

TI has taken its 'C64xx family of DSPs in a new direction with its March introduction of the TMS3206411. Previously introduced 'C64xx family members are among the fastest DSPs available, but they are also among the most expensive. In contrast, the 'C6411 will emphasize cost-efficiency over raw speed: it is projected to operate at 300 MHz and will be priced at $39 in 10,000-unit quantities. The 'C6411 is also expected to be more energy-efficient than existing family members due to its Read more...

Jeff Bier’s Impulse Response—Reinventing the Wheel

In the early days of the automotive industry, every car was a unique, handcrafted specimen—even mundane items like pistons were one-of-a-kind. This changed in 1908, when Cadillac disassembled three Model K's, mixed the parts together, and then built three running cars from the hodgepodge of parts. Today, this feat seems wholly unremarkable—even cars as seemingly dissimilar as Fords and Jaguars often share major components. One of the great lessons of the 20th-century automotive industry is Read more...

DSP-Enhanced FPGAs: Altera vs. Xilinx

On February 11, Altera introduced its all-new Stratix family of FPGAs. These FPGAs feature hard-wired DSP logic blocks; each DSP block can perform up to eight 9-bit, four 18-bit, or one 36-bit multiplications per cycle, with optional accumulation of up to two results. The DSP blocks also contain "pipeline registers;" using these registers increases latency but allows the DSP block to operate at higher clock rates--at over 250 MHz, according to Altera. The main competitor for the Stratix Read more...

More DSP Performance for Motor Control

On February 18, Analog Devices introduced a new line of mixed-signal DSPs, the ADSP-2199x. These new DSPs are based on the ADSP-219x core which contains a 16-bit data path with a single multiply-accumulate (MAC) unit. The first two members of this family, the ADSP-21990 and the ADSP-21991, target motor control applications: both include a 14-bit A/D converter, a three-phase PWM output, and other control-oriented peripherals. With a clock speed of 160 MHz, the ADSP-2199x is one of the Read more...