Freescale Launches 4G Baseband SoC

Submitted by BDTI on Thu, 12/16/2010 - 21:00

The march toward 4G cellular networks is accelerating. For example, Verizon just lit up its LTE network in 38 U.S. cities. But widespread deployment will require lower-cost base stations.  Freescale is aiming to enable lower-cost base stations with its new baseband SoCs, introduced last month on the heels of Texas Instrument’s latest 4G offering. The new Freescale SoCs are based on Freescale’s SC3850 StarCore DSP core that, at 1.2 GHz has just achieved the top fixed-point score on the BDTI DSP Kernel Benchmarks™.

The two chips announced by Freescale  are the MSC8157 and MSC8158. The former is focused on 4G base stations and the latter at 3G base stations. Both designs rely on six SC3850 cores combined with accelerators dedicated to functions such as FFTs and Viterbi encoding and decoding. The new SoCs follow the MSC8156 SoC that has been widely used in 3G base stations, and that also relies on the SC3850 core. Since the new chips use the same DSP core as the MSC8156, they are largely software compatible with the MSC8156; however, the new chips incorporate enhanced accelerators, which mean some code changes will be required for applications using the accelerators.

The new SoCs are being manufactured in the same 45 nm SOI process that Freescale has been using to make the MSC8156. But the new designs boost the clock speed to 1.2 GHz from 1.0 GHz in the prior generation.

The bump in clock speed results in a top fixed-point BDTIsimMark2000™ score of 18,500 for the SC3850 core—up from 15,420 for the 1.0 GHz implementation. With the boost in clock speed, the SC3850 core edges past the recently announced Texas Instruments C66x DSP core, which posted a fixed-point BDTImark2000™ score of 16,690. Note however, that TI chips using this core are already shipping to customers, while samples of the 1.2 GHz Freescale SoCs are due in early 2011.  (The BDTIsimMark2000 and BDTImark2000 are based on the same benchmark suite and are computed identically.  The BDTIsimMark2000 is used when benchmark results are based on simulation, while the BDTImark2000 is used when benchmark results are measured on hardware.)

Freescale’s SoC design is similar to that of the recently-announced TI SoC in that both primarily take a software-defined radio (SDR) approach to cellular baseband processing:  DSP cores handle most tasks, while accelerators handle selected compute-intensive functions. But while the latest TI SoC includes floating-point support in the DSP core, Freescale’s SoC relies on a DSP core that is purely a fixed-point design. In the MSC8157, however, the accelerator that handles multiple-input multiple-output (MIMO) antenna-oriented tasks does include floating-point capabilities.

This MIMO accelerator is one of several accelerators incorporated in the “MAPLE-B” accelerator complex included in the Freescale chips.  The MAPLE-B complex has been enhanced from the version used in the MSC8156 and other prior chips. The block diagram in Figure 1 depicts the latest MAPLE-B implementation; new accelerator functions are bounded by red lines and functions that were upgraded from the prior generation are bounded by yellow lines.


Figure 1. The MAPLE-B accelerator complex

The MAPLE-B MIMO accelerator block supports LTE implementations with as many as eight antennas. (The MSC8158, which targets 3G applications, does not include the MIMO block.)  The MIMO block includes MMSE (minimum mean square error) and MLD (maximum likelihood decoder) equalizers and handles matrix inversions using floating-point arithmetic. Freescale asserts that the MIMO acceleration differentiates its SoC from competing chips, such as TI’s, that rely on floating-point DSP cores to support MIMO. Freescale believes that its hardware approach will give it an edge in meeting demanding latency requirements in the most complex MIMO configurations. Texas Instruments counters that its newest chips can meet the latency requirements of the most complex MIMO implementations, and that MIMO processing is best handled in the DSP core because base station manufacturers often want to implement custom algorithms to differentiate their products. 

The new MAPLE-B design includes three instances of an FFT/DFT accelerator where the prior-generation design included separate FFT and DFT accelerators. Freescale also added a chip-rate accelerator to support 3G wideband CDMA applications. Viterbi and turbo decoding are supported by a single accelerator block. A downlink accelerator block handles turbo encoding.

As with the prior MAPLE-B implementation, two RISC cores manage the allocation of tasks and the flow of data between the DSP cores and the accelerators. A non-blocking switched interconnect fabric connects the DSP cores, memory controllers, and the MAPLE-B complex.

Freescale states that the MSC8157 supports twice the throughput of the MSC8156. The company uses the application scenarios shown in Figure 2 to illustrate the relative capacity. According to Freescale, each MSC8156 can support a single 20 MHz LTE sector, though a design would also require an FPGA to handle antenna processing functions. The MSC8157 directly integrates a CPRI (Common Public Radio Interface) connection to the antenna and can support a 20 MHz LTE sector and two WCDMA sectors with no FPGA required, according to Freescale.


Figure 2

Freescale claims that its new SoCs will roughly deliver 50% savings in cost and power consumption relative to its previous-generation offering. The company plans to sample the new products to tier-one customers in the first quarter of 2011, with volume shipments beginning in late 2011. 

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