Xilinx Announces Next-Generation 28 nm FPGA Families

Submitted by BDTI on Thu, 07/29/2010 - 19:00

Xilinx recently announced its next-generation “7 series” FPGAs, featuring new power-saving features as well as increased capacity and performance.  The series will be composed of three chip families, all fabricated in TSMC’s high-k metal gate (HKMG) 28 nm technology.  All three families will use the same logic cells, block RAMs, DSP slices, and I/O cells.  Compared to existing 40 nm Xilinx devices, Xilinx claims that, in typical applications, the new FPGAs will reduce power consumption by 50, deliver the same performance at 50% lower cost, or offer twice the performance in a single chip.  The forthcoming ARM-based CPU-FPGA platform described here will be part of the new 7 series FPGAs.

In an interview focused on the 7 series FPGAs, Vin Ratford, Xilinx’s senior marketing VP, spoke extensively about power-saving technologies used in the new chips.  Of course, some power savings are obtained simply by moving from a supply voltage of 1.0 volts in 40 nm technology to 0.9 volts in 28 nm (this should contribute about 20% savings in core logic dissipation).  Some blocks other than logic cells, such as the configuration memory, have further reduced voltage requirement to save power.   Additional features intended to reduce power include voltage islands to enable turning off power to unused blocks (notably block RAMs), finer-grained clock gating, and tweaks to the architecture of fixed-function circuits within the FPGA.

As mentioned above, the three new families (named Artix-7, Kintex-7 and Virtex-7) will all be manufactured in the same process.  This is a change from Xilinx’s previous strategy, in which lower-cost Spartan FPGAs used a 45 nm low-power process and higher-capacity Virtex devices used a 40 nm high-performance process.   The Artix-7 family is designed for low-power, low-cost products such as portable ultrasound, digital SLR cameras, and portable software-defined radio transceivers.  Xilinx states that Artix-7 devices will be 30% faster than Spartan-6 devices with 35% lower prices for similar capacities.  The Kintex-7 family targets applications where the emphasis is on cost-performance, including wireless base stations, video displays, and avionics.  Virtex-7 devices are intended for very high-performance systems.  Xilinx expects that the improved energy efficiency of the Virtex-7 devices will enable larger designs than would have been possible with previous generation FPGAs.  Virtex-7 devices will feature up to two million logic cells.  Additional details of the 7 series FPGAs are summarized in Table 1, below.

Altera also recently announced its 28 nm Stratix V family, which will compete with some of the new Xilinx devices—namely, the higher end Kintex-7 devices and the Virtex-7 devices.  Altera will continue to separately develop its lower-cost, smaller capacity Cyclone family and mid-range Arria family.  The Xilinx 7 series and Stratix V families share as many features as separate them—both families will sample in early 2011, are manufactured in the TSMC HKMG process, have up to about 75 transceivers (including some 12.5 Gbps transceivers), offer between 3,500 and 4,000 DSP slices, and provide over 50 Mbits of embedded memory.  Xilinx claims an edge on several features, including logic cells (2 million vs. 1.1 million for Altera), peak serial bandwidth (1.9 Tbps vs. 1.6 Tbps for Altera), PCI Express interfaces (8 rather than 4 PCI Express Gen 3 interfaces), DDR DRAM bandwidth (2,133 Mbps vs. 1,600 Mbps for Altera) and hard-wired DSP MACs (2,350 GMACS vs. 1,840 for Altera).  Altera’s key unique claims are in areas such as its HardCopy ASIC-conversion program, partial reconfiguration capability for modular designs, and variable-precision DSP blocks (described here).  FPGAs are increasingly becoming complex SoCs, containing not only lots of programmable logic, but also a vast number of sophisticated, specialized structures.  This makes comparing competing offerings more difficult, and means that the best choice may differ dramatically depending on details of the application requirement.

A summary of the newly announced 28 nm Altera and Xilinx FPGAs is shown below:



Logic Cells (Kgates)


Transceivers (number / Gbps)

Total Memory (Mbits)


Stratix V GT

425 – 622


4 / 28

32 / 12.5

45 – 50

Stratix V GX

200 – 534

188 – 306

24 – 66 / 12.5

20 – 50

Stratix V GS

563 – 1,100

1,620 – 1,840

27 / 12.5

32 – 34



18 – 352

40 – 700

4 / 3.7

1 – 16


30 – 407

120 - 1,848

16 / 10.3

2.5 – 34


285 – 2,443

420 – 2,350

72 / 13.1 ¹

18 - 77

Table 1: Summary of Altera and Xilinx 28 nm FPGA families

¹ 28 Gbps transceivers will be added to the family at a later date, according to Xilinx.

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