Jeff Bier’s Impulse Response—High-Level Synthesis Tools for FPGAs: A Disruptive Technology?

Submitted by Jeff Bier on Wed, 04/21/2010 - 17:00

In 2002, BDTI published the first rigorous, independent benchmarking study comparing the signal processing capabilities of high-end FPGAs to those of high-performance DSP processors. We benchmarked both technologies on the same demanding, highly-parallelizable multi-channel wireless application, and we looked at how many channels could be supported on each chip and the corresponding cost per channel.   We knew that FPGAs had begun to find use as high-end signal processing engines, but we were blown away by how much of a throughput advantage they actually had—the FPGAs we looked at achieved orders of magnitude higher throughput than the DSP chips on our benchmark. And not only that, the FPGAs showed a huge cost-performance advantage over the DSP processors.   When we repeated this experiment with newer silicon in 2006, the results were very similar.  It was enough to make a person question why anyone would still use processors for these kinds of applications.

One answer was that it was really hard to map an application onto an FPGA compared to mapping it onto a processor. On a processor, you could start off by simply compiling your reference C code.  Even if it wouldn’t run very fast, at least it would run. So your starting point was a working version of your application on your processor. With an FPGA, in contrast, you’d spend months just getting to that initial running version. 

This naturally led us to ponder the question: Is there a way to get the performance of an FPGA with the ease-of-use of a processor?  One obvious candidate for bridging this gap is high-level synthesis tools.  These tools consume a high-level language description of desired functionality, and produce a register-transfer-level description of a hardware implementation of that functionality—sort of like compilers for FPGAs.  The history of this technology is not encouraging, though.  For decades, very smart people have been developing high-level synthesis tools for use in chip design, without widespread success.  As a result, many engineers are skeptical that such tools will ever succeed.  On the other hand, over the past few years, we’ve been hearing from some very savvy designers that they’re using high-level synthesis tools with good results.  This piqued our curiosity, and in early 2009 we launched a new evaluation program, the BDTI High-Level Synthesis Tool Certification Program.

In January, BDTI released the first results of this new evaluation program. Initially we have evaluated two high-level synthesis tools: Synfora’s PICO and AutoESL’s AutoPilot. These tools can take C code as their input and generate device-specific RTL for an FPGA.  Using one video application and one wireless application we looked at the throughput of the synthesized FPGA implementations compared to that of the same application implemented on a mainstream DSP processor, and we looked at the efficiency (in terms of resource usage) of the synthesized version compared to that of a hand-crafted RTL design on the same FPGA. 

What we found was pretty amazing. For our highly parallelizable DSP applications, the high-level synthesis tools yielded FPGA implementations that have much higher performance than that of the DSP processor (both in terms of throughput and cost-performance).  Even more surprising, the efficiency of the synthesized implementations was as good as hand-coded RTL design, and the development effort was comparable to using a DSP processor.

Now, these tools are not perfect.  For one thing, the user is largely responsible for taking the synthesized RTL design through the traditional RTL synthesis and place-and-route tools.  This can be a daunting process for engineers without FPGA design experience.  For another, we don’t yet know how the performance of the high-level synthesis tools holds up with much larger applications. 

Nevertheless, I believe that high-level synthesis tools are a disruptive technology.  In many applications and organizations, I expect that these tools will significantly alter the trade-offs when choosing between a DSP processor and an FPGA.  I also expect that they will eventually open up a range of new applications for FPGAs.  Companies who couldn’t have used FPGAs as processing engines before (due to lack of time or expertise) may soon be able to.

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