High data rates pose a number of system design challenges. They require lots of I/O and an extremely fast processor or FPGA, they need lots of memory for storage and buffering, and they eat power as data gets shipped all over the system. That’s why, when high-speed data gets to a processor, often the first thing that’s done is to compress it. But what if you could compress the data before it ever gets to the processor and before it gets shipped around the system? What if you could compress it right at the A/D, where the data first comes in? That’s the clever idea that Samplify Systems hopes to build a business on.
Samplify, a start-up based in Santa Clara, was originally created to sell FPGA-based compression IP and proprietary software-based compression algorithms. But somewhere along the way the company came up with the idea of mating its compression IP with a high-speed A/D converter, and selling the whole thing in a single chip. Thus, in October of this year, Samplify announced that it had morphed into a fabless semiconductor vendor offering a family of high performance A/D converters with integrated real-time data compression. (The company does not yet offer DAC-plus-decompression chips, but says that it plans to do so in the future.)
Samplify’s SAM1600 family includes three 12-bit, 65 Msample/second ADCs. The SAM1600 and SAM1610 (shown in Figure 1) have sixteen channels, while the SAM1605 has eight. The ‘1610 and ‘1605 incorporate Samplify’s proprietary Prism compression algorithm, which compresses data using one of three modes: lossless; a lossy mode that maintains a fixed compression ratio; and a lossy mode that maintains a fixed SNR. According to Samplify, the on-board digital processing doesn’t affect the ADC’s noise characteristics; SNR is 68.5 dB.
The ‘1600 chip doesn’t include Prism and is intended for users who don’t need compression but want a high performance, low-power ADC. Power consumption for the 16-channel, 12-bit device is 44 mW per channel.
Figure 1. Samplify’s SAM1610 chip (figure courtesy of Samplify).
All three of the chips include Samplify’s “port concentration technology,” which is designed to maximize the use of LVDS outputs by running them at full speed all the time. According to Samplify, this technique enables the chips to concentrate data from, for example, four 12-bit ADCs operating at 50 MSPS (600 Mbps output data rate per channel) onto three LVDS outputs running at 800 Mbps for a 25% reduction in I/O pins – even before including any compression. Samplify says that with the addition of Prism compression, the chips can achieve up to a 75% reduction in I/O pins compared to a typical ADC.
Samplify’s chips are now sampling, with 1K pricing set at $64.00, $39.50, and $79.00 for the ‘1600, ‘1605, and ‘1610 respectively. This pricing includes a royalty-free license to Prism decompression
Initial target applications include ultrasound (both portable and high-end consoles), CT scanners, and 4G wireless base stations that use OFDM-based technologies. It’s not hard to imagine that there will be many other high-data-rate applications that could benefit from this approach, which Samplify describes as “A disruptive technology for intelligent data conversion.” Ultimately Samplify expects to incorporate its ADC-compression combo into ASSPs for high-data rate applications. The company hopes to enable applications that are currently implemented exclusively in analog (because of prohibitively high data rates) to find their way into the digital domain—with all the advantages that digitization confers.
BDTI recently wrote that embedded processor companies would do well to develop or acquire their own proprietary algorithms as a way to add value and stay competitive in the coming decade. Samplify isn’t a processor company, but it’s making good use of the same idea.