XMOS Semiconductor, a fabless semiconductor and software provider based in
A key feature of XMOS’ approach involves peripherals. Instead of using fixed-function hardware to implement a fixed set of on-chip peripherals (e.g., a USB interface), XMOS chips have generic pins connected to the array of tiles. On-chip peripherals are implemented in software running on those tiles. The tiles are designed to give tightly coupled, speedy software access to the 64 pins available to each tile. Thus, the choice of peripherals is under software control, since a change in software can change the function of the pins. (The XS-1 does not support interfaces, such as IEEE 1394, requiring special voltages or currents.)
Each tile provides a number of ports; a port is a hardware facility supporting timers for time-stamps on inputs, and buffering for inputs and outputs. The time stamps are available to software running on the tile. The ports vary in size from 1 to 32 bits. All of the ports are multiplexed onto the 64 pins associated with each tile.
Each tile can support up to eight threads, with each thread handling programmed peripherals or other code such as applications. Each thread has access to 16 32-bit registers. Tiles support 32-bit arithmetic including a single-cycle 32 × 32 ≥ 64-bit multiply-accumulate (with the output written into two registers). Besides the multiply-accumulate, there is support in the instruction set for other DSP operations such as bit-reversed addressing.
Each chip also provides what XMOS calls the XLink switching fabric to enable communication between cores and threads. The switching fabric implements up to 32 channels of contention-free on-chip thread-to-thread communication. There is hardware support for off-chip XLink ports so that threads on separate XMOS chips can communicate. There is also support for thread synchronization and semaphore passing.
Initial chips feature 64 kbytes of memory per tile for instructions and data. Currently there is no other on-chip RAM. Likewise there is currently no dedicated hardware for an external memory interface on the chip. External memory interfaces can of course be assembled using ports and I/O pins.
As with other programmable chips, XMOS foresees the possibility of system developers upgrading software in the field, which could open the chip up to hacking and reverse engineering attacks. To counter this, the XS-1 family offers 8 Kbytes of one-time-programmable (OTP) memory per tile. Also, one or more of the tiles can be set up to be isolated from the outside world, communicating only over XLink channels to other tiles. The program and operation of such an isolated tile would not be directly accessible from outside the chip.
XMOS tiles are programmed in C, C++, and in a proprietary C variant developed by XMOS and called XC (a code sample is available). The XC language, which is largely C, contains keywords and facilities for working with the ports and channels mentioned above. The XC language also contains facilities for timing, such as reading a port timer mentioned above, or waiting until a specific time is reached. Instead of writing a C compiler from scratch, XMOS uses the CoSy compiler development system from Ace Associated Computer Experts. In addition to the compiler, the XMOS toolset offers a simulator, debugger, and profiler. For now, the programmer must partition tasks by hand among threads and tiles.
The XS-1 can boot from the OTP on-chip memory mentioned above or via the JTAG interface. In addition there is a small ROM which implements (using pins and software) an SPI port through which the chip can boot from external memory.
Initially, XMOS has focused its software development effort on I/O interfaces. A software library of interfaces will be available from XMOS with the release of the first chips. In the long run, XMOS expects customers to develop their own C and XC code, and for third parties to develop and license IP blocks. BDTI believes that the initial offering will not include a large number of higher-level software modules such as audio and video codecs.
Four-tile prototype silicon for the first members of the XS-1 product family was demonstrated at CES in January and will be shown at the Embedded Systems Conference in
Similarly, XMOS has not released power consumption figures. Power-saving features, such as clock-gated cores, and software control of clock frequency, have been incorporated into the design. However, since the initial chips are not being fabricated in a low-power process, BDTI does not expect that the initial focus of XMOS' marketing will be on portable devices. BDTI expects XMOS to release processors manufactured in a low-power process, targeted toward portable applications, at a future date.
Although many processor-centric chips contain general-purpose I/O pins that can be programmed, in general peripherals such as UARTs and Ethernet ports have remained in hardware, leaving users of off-the-shelf processor chips with limited flexibility in selection of peripherals. In contrast, FPGAs have long provided flexible I/O capabilities. But for most system developers, designing with an FPGA means working with relatively low-level, hardware description language techniques that are quite different from the software-oriented approaches typically used with processors.
XMOS believes that it has staked out an attractive middle ground between traditional processor chips and processor-based SoCs on the one hand, and FPGAs on the other. Compared with traditional processor-based chips, the XMOS approach promises much more flexibility in I/O interfaces. Compared with FPGAs, XMOS believes that its processor-centric architecture will be a more attractive development target for many system developers. And XMOS believes that it will be able to deliver more processor performance per dollar relative to FPGAs because the XMOS processor cores are implemented directly in silicon rather than using programmable logic (which is the approach used with most processors incorporated into FPGAs). Based on an initial analysis of the XMOS architecture, BDTI believes that XMOS may be able to deliver on these promises. The proof, of course, will have to wait for the actual XMOS silicon products—and their associated price, power consumption and application development support.