Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1. (The middle of the family range is filled out by the AV 404V, AV 406V, and AV 407V) are intended for compression-centric applications such as camera phones, portable media players, DVB-H and DVD players.
The new subsystems are ARC’s first to target high-quality video encode, which ARC believes has become a requirement of many multimedia applications. All AV 40xV subsystems include a CPU core and a two-dimensional DMA engine. They also include varying assortments of SIMD media coprocessors as well as hardware accelerators for motion estimation, entropy encoding, and entropy decoding. For instance, the AV 402V, targeting low-resolution cell phones, features one SIMD media coprocessor and one entropy encoding accelerator; the AV 417V, targeting high-quality video, features two SIMD media coprocessors and all three accelerators. ARC also offers software for many video, imaging, and audio codecs.
ARC’s initial business focus was on configurable RISC CPUs, and the new video subsystems hew to that heritage in two ways. First, each subsystem includes an ARC700 family CPU. Second, each subsystem is configurable by the licensee in a few respects. For example, licensees can select among several ARC700 CPU family members, and can add custom instructions to the CPU and tweak the cache size.
According to ARC, the AV 417V can encode H.264 Baseline Profile (D1 resolution, 30 fps, 10 Mbps) at 200 MHz, and is also capable of MPEG-4 Simple Profile/Advanced Simple Profile encode, H.264 Baseline Profile decode, and MPEG-4 Advanced Simple Profile decode. ARC estimates the die size of the AV 417V to be 4.95 sq. mm (post-layout), including 32 KB instruction and data caches, in a 90 nm “G” process using Virage libraries.
The AV40xV subsystems include a capability that ARC refers to as “dynamic adaptive encoding.” While ARC hasn’t disclosed details due to patent considerations, it claims that this feature enables the subsystems to dynamically adapt encoded video quality, compression rate, clock rate, power consumption, and bus usage in response to parameters such as input scene complexity and available battery charge. Adjusting codec settings (such as quantization) to achieve quality and bit-rate tradeoffs isn’t uncommon among video encoders. However, ARC believes its technique is distinctive in that, on a frame by frame basis, it automatically varies which “tools” (algorithmic options within the encoder) are used in response to system constraints (such as remaining battery charge).
Vendors creating architectures for video often strive to balance conflicting demands of efficiency and flexibility. Heterogeneous programmable architectures such as ARC’s aim to provide the flexibility of DSPs or CPUs with efficiency nearing that of hardwired solutions. Such architectures can be difficult to program efficiently, however, typically requiring a mix of C and assembly programming for maximum performance. ARC expects most of its customers to use ARC’s codecs while adding pre- or post-processing functionality; to ease programming effort, it also provides optimized basic function libraries and training.
The announced ARC subsystems will compete against a growing field of video processing silicon IP offerings. Notable competitors include Tensilica’s 388VDO engines (featured in the July 2007 InsideDSP), CEVA’s MM2000 multimedia platform, and hardwired video solutions from Imagination Technologies and Hantro (recently acquired by On2).
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