Telairity Chip Targets High-Definition Video Encoding

Submitted by BDTI on Mon, 08/15/2005 - 19:00

Today fabless chip startup Telairity introduced its first chip, the T1P2000. The chip targets high-definition H.264 video encoding in applications such as broadcast encoders, video servers, and video authoring systems.

The T1P2000 is based on the Telairity TVP400 processor core. The computational demands of high-definition H.264 encoding are enormous, and the architecture of the T1P2000 reflects these tough demands. The T1P2000 includes five Telairity TVP400 processor cores as well as a variety of video-oriented peripherals.

The TVP400 cores operate at 668.25 MHz, which is nine times the 74.25 MHz clock rate commonly used by high-definition video streams. It is difficult to compare the performance of the TVP400 processor cores to the performance of competing architectures because the TVP400 uses an unusual vector architecture—an approach common in supercomputers, but rare in embedded applications. (For an overview of the TVP400 architecture, see “Telairity Introduces Vector DSP Core” in the September 2003 edition of DSP Insider.) However, a crude analysis of multiply-accumulate (MAC) throughput shows that each TVP400 can complete four 16-bit MACs per cycle—comparable to the capabilities of leading DSP architectures such as the Texas Instruments ‘C64x.

In addition to the five TVP400 cores, the T1P2000 includes a variety of video-oriented peripherals. These include video input and output ports that support high-definition ITU/BT-709 video streams as well as 5 SPI-compatible serial ports. The T1P2000 also includes a variety of hardware that reduces the load on the TVP400 cores. This includes hardware to detect control signals in the input stream, as well as hardware that strips ancillary data such as closed captioning information from the input video stream. On the output side, the T1P2000 includes bit packing hardware.

Telairity believes customers will need four to eight T1P2000 chips and a $60 FPGA to implement a real-time, high-definition H.264 encoder. (The number of T1P2000 chips depends on the desired video quality.) In contrast, Telairity believes that an equivalent DSP-based system would require a dozen or more DSPs as well as several expensive FPGAs. BDTI has not investigated these claims, but it is certainly the case that implementing a high-definition H.264 encoder on today’s DSPs would require several chips.

Telairity believes its solution has a significant cost advantage over competing DSP-based solutions. BDTI does not have enough data to verify this claim, but the chip does appear to be more cost-effective than some high-speed DSPs. As a point of comparison, the five-core 668.25 MHz T1P2000 costs $425, compared to $189 for the single core, 1 GHz ‘C6414T. A crude cost-performance comparison suggests that the T1P2000 is more cost effective than the ‘C6414T. However, the T1P2000 appears to be less cost-effective than slower ‘C64x parts.

Samples of the T1P2000 are available now, with production quantities expected to be available in Q4 2005. The T1P2000 is packaged in the 1156-pin FCBGA (flip chip ball grid array) package.

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