Three new DSP architectures were presented at the Embedded Processor Forum in San Jose last month. All three architectures are heterogeneous, i.e., they each combine a DSP with other performance enhancing hardware. All three architectures also target communications applications.
It is already common in communications applications to find boards that combine DSPs, general-purpose processors, reconfigurable logic, and ASICs, albeit with each on a separate chip. As the potential for integration increases and these different elements can be included on the same die, there will be a great demand to capitalize on the benefits of doing so-reduced cost, size, and power consumption foremost among these. The three architectures presented at EPF suggest that this trend is already underway.
The first device presented at EPF was the Texas Instruments TMS320C6416. This chip was announced earlier this year and combines TI's 'C64xx DSP core with two coprocessors. A full analysis of the 'C64xx core is available in Buyer's Guide to DSP Processors, 2001 edition.
The second architecture was BAZIL, which was jointly developed by LSI Logic and Ericsson. BAZIL targets communications infrastructure equipment by integrating LSI's "ZSP" DSP core with two ePLCs (reconfigurable logic blocks). Subtasks of an application are mapped onto either the ZSP core or an ePLC according to the complexity and computational demands of the sub-task. The ePLC can handle the more computationally demanding functions that are less complex and more repetitive while the ZSP core takes care of the more complex but less computationally demanding functions.
LSI licensed the ePLC technology from Adaptive Silicon, and this acquisition has neatly rounded out LSI's IP portfolio for communications applications—it now offers reconfigurable logic, DSP cores, general-purpose processor cores, and ASIC capability. This puts LSI in a strong position: it can offer ASIC customers a diverse array of building blocks; moreover, LSI can draw from these elements in its own ASSP designs. If nothing else, BAZIL is good proof of concept for LSI's integration capabilities.
But how effective is this combination? LSI presented FFT benchmark data, but the data suggests that on this benchmark the ZSP and two ePLCs would not be as fast as, e.g., Motorola's SC140-based MSC8102. Speed, however, was probably not LSI's only consideration; there was, after all, a development partner, and Ericsson likely achieved its application-specific goals with BAZIL.
The third DSP architecture shown at EPF was the new SkyCore from STMicroelectronics. This heterogeneous design combines an ST120 DSP and an ARM7 general-purpose processor and targets automotive media applications, e.g., receiving digital broadcasts in a car. The SkyCore is a highly integrated SoC with many specialized I/O interfaces and on-chip peripherals.
An interesting question about the SkyCore is why it uses an ARM7 when the ST120 is marketed as having strong general-purpose processing capabilities in addition to its DSP features. Perhaps the ARM7 was used in an effort to optimize energy consumption: the ST120 is a fairly heavyweight processor that requires fast memory, while the ARM7 can get by with much slower memory. When low power consumption is required the DSP could simply be shut down, with the ARM7 performing interface and supervisory tasks.
As communications products continue to demand increased processor power while simultaneously demanding reduced cost, size, and energy consumption, heterogeneous designs like these will cease to have novelty status. Rather, they will become the mainstream solution.
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