Processors

Freescale has announced a new high-performance DSP product line, the MSC825x, incorporating up to six StarCore SC3850 DSP cores at up to 1 GHz.  Unlike other high-performance DSPs introduced by Freescale in recent years—which were aimed almost exclusively at wireless infrastructure
Xilinx recently unveiled a new chip architecture integrating an ARM processor with an FPGA fabric. This platform centers around a dual-core ARM Cortex-A9 processor complex, including hardened memory interfaces and peripherals.  The platform architecture, shown in Figure 1, is intended to
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Analog Devices, Inc (ADI) has announced new members of its floating-point SHARC processor family featuring lower prices and offering LQFP packages, which are easier to use in older, lower-cost manufacturing facilities. The new SHARC products target digital audio, industrial, automotive, and
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CEVA recently announced its third-generation video processor IP offering.  The CEVA-MM3000™ is a programmable subsystem which is designed to support video decode and encode using many video standards, including H.264, VC1, RealVideo and AVS at resolutions up to 1080p (1920×1080
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TI has unveiled a new chip-level architecture for high-performance, multi-core DSP-processor-based SoCs.  Most notable among its features are new on-chip and chip-to-chip interconnection mechanisms, an upgraded high-performance DSP core, and both hardware and tools support for programming
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Analog Devices, Inc. (ADI) has announced new members of the Blackfin processor family targeting control-loop applications.  The new BF50x parts sport a much larger “executable” flash in place of the serial flash offered in earlier Blackfin chips, and integrate a 12-bit
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In October of 2007, I wrote a column called “ When Worlds Collide ,” which was about NVIDIA’s emerging strategy of offering “general-purpose GPUs.”  At the time, I thought it was interesting that NVIDIA had begun to move beyond graphics applications to target
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This month CEVA announced significant improvements to its software tool suite.  Collectively, the new tools and features are dubbed the CEVA Application Optimizer, and are part of the CEVA-Toolbox software development suite.  CEVA describes these capabilities as providing an
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This month MIPS introduced two new cores, the M14K and M14Kc, that are based on a new instruction set architecture called microMIPS.  MicroMIPS uses a mixed-width 16/32-bit instruction set to improve code density relative to the MIPS32 instruction set architecture. In general, processors
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Posted in Processors, Video
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This month fabless semiconductor start-up Quartics introduced the QV1721, a video coprocessor SoC targeting applications such as netbook PCs, set-top boxes and high-definition televisions.  The QV1721 is intended to be used to offload demanding video tasks from the main CPU in a system. The