FPGA Start-Up Tabula Exits Stealth Mode, Unveils “3-D” Architecture and First Devices

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FPGA start-up Tabula recently emerged from stealth mode and disclosed details of its architecture, dubbed Spacetime, and product line, called the ABAX family. Tabula’s products are intended to compete against existing high-end FPGAs by offering higher density with the same design methodology.  Tabula is initially aiming its chips at network, wireless, and telecom infrastructure markets–all sweet spots for programmable logic.  These markets are characterized by a need for programmability due to rapidly changing standards, unit volumes too small to attract ASSP or ASIC competition, and relatively high gross margins for semiconductor suppliers.

In conventional FPGAs, each programmable logic element (often referred to as a “look-up-table” or “LUT”) performs a single function.  In contrast, in Tabula’s ABAX chips, each LUT performs up to eight functions in a time-multiplexed manner.  Since the ABAX logic elements run at 1.6 GHz, they can perform each of these 8 time-multiplexed user functions at a 200 MHz “user” clock speed.  Tabula refers to this as enabling a third dimension (time) in the FPGA.

Tabula’s architecture is a novel attempt to solve the interconnect bottleneck in FPGAs.  By using each LUT and memory block multiple times, Tabula claims that less interconnect (wire length) is required.  Tabula relies on transparent latches embedded in the chip’s interconnect to handle both routing and temporary state storage between time slices (called folds by Tabula). 

Similar to the time-multiplexing of LUTs, Tabula uses single-ported memories in a time-multiplexed way so that each memory block provides a separate virtual port for each fold.  Hence, what is physically a single-ported memory takes on the functionality of a multi-ported memory.  These memories can be used for sharing data between folds or individually allocated to the folds.  Tabula claims this memory architecture contributes to its density advantage over traditional FPGAs, which rely on dual-ported memory blocks.

Tabula’s ABAX product line consists of four chips offering between 220K and 630K virtual 4-input LUTs.  All family members feature 5.5 Mbytes of RAM, and use the same 1936-pin BGA package with 920 parallel I/O pins and 48 high speed I/O pins which support a variety of SerDes standards.  In addition, the largest device offers 1,280 virtual 18-bit×18-bit multipliers.  Comparing capacity of FPGAs that use different architectures of FPGA devices must be done with caution.  Table 1 provides basic data on the largest device families from Altera, Xilinx and Tabula.

Company

Product Line

Part

Type of LUT

Number of LUTS

18×18 Multipliers

MB RAM

Altera

Stratix IV

EP4SGX530

8-input

      212K

      1024

     8.3

Xilinx

Virtex-6

XC6VLX760

6-input

      474K

       864¹

   20.7

Tabula

ABAX

A1EC06

4-input

      630K²

    1280²

    5.5

¹ 25×18 multipliers ² Virtual resources

Tabula provides logic synthesis, place and route, and configuration stream generator tools.  Tabula claims that its design flow is virtually identical to standard FPGA tool flows.  If this is the case, Tabula should be able to quickly estimate and verify customer application performance in the Tabula devices, which could make its selling cycle shorter than those of other programmable logic vendors with less compatible tool flows.  Tabula’s ultimate performance advantage will likely come down to the strength of the Spacetime architecture, as well as how well Tabula has balanced critical design decisions such as the relative amounts of logic, multipliers, memory, and I/O.  Tabula has had some opportunity to evaluate these tradeoffs using its earlier test chips; time and multiple applications will show definitively how well the company has done.

Tabula’s performance claims are focused on performance per area, and, by extension, performance per price relative to the biggest programmable logic vendors, Altera and Xilinx.  Tabula claims 3.7X performance density (measured in throughput per mm²) on a signal processing benchmark (2K FFT with LTE parameters), compared with a Xilinx Virtex-6.  By extrapolating from this result, Tabula claims 2X performance at equivalent price levels in the same process. 

Tabula’s ability, as a startup, to design chips in TSMC’s new 40 nm process speaks to its industry connections.  Tabula has raised $106M to date, including $24M in November 2008, a time when other programmable logic startups (such as Ambric and MathStar) closed their doors.  A few other FPGA startups remain in the field, including Achronix (focused on highest speed), Abound Logic (formerly M2000 and focused on largest capacity) and SiliconBlue (focused on low power).  In addition, Tier Logic recently disclosed another 3-d architecture (with the third dimension being space) here.

Tabula says that its prototype chips are in the hands of a few early customers, with samples expected in the third quarter 2010.  Prices for ABAX chips range from $105 to $200 in 1,000 unit quantities.