CEVA Rolls Out New Programmable Multimedia IP Core for HD Video

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CEVA recently announced its third-generation video processor IP offering.  The CEVA-MM3000™ is a programmable subsystem which is designed to support video decode and encode using many video standards, including H.264, VC1, RealVideo and AVS at resolutions up to 1080p (1920×1080 resolution at 30 or 60 frames per second). The CEVA-MM3000 is designed for use in several classes of digital media products including smartphones, tablets, Blu-ray DVD players and set-top boxes.

The CEVA-MM3000 subsystem is based on a fully programmable multi-core, heterogeneous architecture which uses a task scheduler to control two types of core engines–stream processors and vector processors.  Stream processors are intended to run outer-loop control code as well as bitstream processing functions such as entropy coding.  Vector processors are intended to run pixel-rate operations such as color space conversion or motion-detection algorithms.  The CEVA-MM3300 can be scaled by selecting the number of each type of processing unit and configuring memory sizes.  According to CEVA, single stream processor and a single vector processor will support 1080p decoding and 720p encoding using any codec standard, while the maximum configuration of four of each type of processor will support encoding at 1080p 60 fps or decoding of multiple simultaneous channels of 1080p 60 fps.

CEVA believes that its programmable platform will allow customers to differentiate products through new algorithms for pre- and post-processing video functions, and intelligent video processing such as face recognition and object tracking.  For example, CEVA anticipates that these capabilities will enable handset vendors to create augmented reality games and mapping overlays. Since it is a programmable platform, chips based on the CEVA-MM3300 can be updated in the field to support new codecs or other functions.  New video codecs continue to emerge, such as H.264 SVC (scalable video coding, supporting adaptive bitrates) and MVC (multiview video coding, supporting 3D displays).  Customers’ ability to support new functionality will, of course, depend on being able to fit it within the available processing performance.  The strength of CEVA’s programming tools will also be critical, given the complexity of developing highly optimized software for a heterogeneous multi-core architecture. 

Historically, most silicon IP offerings for video processing have used more specialized hardware accelerator blocks—a less flexible approach appropriate for devices like digital camcorders or DVD players which support a pre-defined set of processing functions and standards.  However, this approach does not work as well in devices intended to support the latest Internet content, which is published using a rapidly changing set of codecs.  Notable silicon IP providers with hardware accelerators include Chips & Media and Hantro (acquired by On2 and now part of Google).  ARM offers both hardware acceleration using its Mali-VE core as well as the ability to process video in software using the Cortex-A8 and Cortex-A9 CPUs with the NEON SIMD extensions.

One potential pitfall of a fully programmable solution is power consumption.  However, if vendor-published figures are accurate, a comparison between the CEVA-MM3000 and the ARM Mali-VE6 suggests that CEVA-MM3000 power consumption may be in the same range as that of more specialized solutions.  ARM specifies that Mali-VE6 is capable of H.264 Main Profile decode at 1080p30 in 45 nm process using 100 mW, while CEVA states the MM3000 core is capable of H.264 High Profile decode at 1080p in 40 nm process using 150 mW.  

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