- The CEVA-XM6 Vision Processor Core Boosts Performance for Embedded Deep Learning Applications
- CEVA Second-generation Deep Learning Toolset Supports Additional Frameworks and Topologies
- HSA Foundation Aims for Broader Adoption of Coherent Memory Standard for Heterogeneous Processors
- Movidius' Fathom Enables Embedded Deep Learning
- Case Study: From Platform Selection to Optimized Application: Vision System Design Success
BDTI Unveils High-Level Synthesis Tools Certification Program Results
This week BDTI released the first results from its High-Level Synthesis Tools Certification Program (HLSTCP). The first tools to achieve certification are AutoESL’s AutoPilot and Synfora’s PICO. Additional certifications will be released on an ongoing basis, as agreements with tool vendors allow. The HLSTCP helps engineers and managers understand the capabilities of high-level synthesis (HLS) tools and assess when to consider these tools for their designs. HLS tool vendors can use the program to validate and improve the quality of results and productivity provided by their tools. (HLS tools are also referred to as electronic system level [ESL] synthesis, C synthesis, behavioral synthesis, or algorithmic synthesis tools.)
High-level synthesis tools are used to synthesize a hardware design at the register transfer level (in Verilog or VHDL), starting from a high-level language description of the required functionality. Depending on the tool, high level languages may include C, C++, SystemC, M (MATLAB), or proprietary languages. When starting with purely behavioral high-level language code, HLS tools generally require the user to modify the high-level language code to achieve good results.
In 2007, BDTI published FPGAs for DSP, a seminal study showing that FPGAs can achieve up to 100x better performance and 30x better cost/performance compared to DSP processors on some demanding, highly parallelizable digital signal processing applications. Those earlier results were obtained using traditional FPGA design methods, beginning with hand-written RTL descriptions. Such approaches are much more time-consuming than application software development for embedded processors. Is it possible to obtain similar levels of performance from FPGAs with much less effort using high-level synthesis? How does the performance and efficiency of synthesized designs compare to that of traditional designs? BDTI’s certification program answers these questions. More specifically, the program compares FPGA design using high-level synthesis tools to two more established alternatives:
- RTL FPGA design using hardware description languages
- DSP processor software development
The program compares the effectiveness of these approaches in terms of quality of results and usability (skills required, ease-of-use and productivity).
The BDTI HLSTCP uses two example applications to represent a wide range of DSP applications. The BDTI Optical Flow application represents a range of video processing algorithms. It operates on 720p video (1280 x 720 progressive scan) at 60 frames per second, analyzing the apparent motion in a video scene. The BDTI DQPSK Receiver application is a fully functional wireless communications receiver implementing differential quadrature phase shift keying (DQPSK) and operating at approximately 5 Mbps.
Synfora PICO and AutoESL AutoPilot achieved excellent results on the certification program. Both tools, used in conjunction with Xilinx RTL tools, produced high-quality designs and delivered good productivity. For example, the FPGA resource use for the high-level synthesis-based FPGA implementations of the BDTI DQPSK Receiver application were virtually equivalent to that of a traditional hand-written RTL implementation created by an experienced designer. Both HLS tool based FPGA implementations of the Optical Flow application achieved cost/performance 30x better than the DSP processor.
Perhaps most surprising, the total effort required for BDTI engineers to implement the BDTI Optical Flow application on the FPGA using the high-level synthesis flows was very similar to that required for the software implementation of this application on a DSP processor. It’s important to note, however, that relative effort levels will vary by application and that different skills are required for these different classes of design flows. In particular the FPGA high-level synthesis tools do not eliminate the need for RTL design skills; the HLS user must work intensively with the RTL tools (logic synthesis, placement, timing analysis, etc.) to transform the synthesized RTL design into a working FPGA implementation.
The HLSTCP results for the first two tools to achieve certification—AutoESL’s AutoPilot and Synfora’s PICO are available on BDTI’s website. Additional tool evaluations will be performed and made available as agreements with tool vendors allow.