- HP, PayPal Give ARM-plus-DSP Chip a (Moon)Shot
- New Chips Expand Automotive Safety Capabilities
- Jeff Bier’s Impulse Response—"We're Number One!"
- ON Semiconductor's Hearing Aid SoCs: Distributed Performance That's Easy on Batteries
- Case Study: BDTI's Expert, Independent Analysis Enables Optimum Vision Processor Selection
ARM Launches Cortex-A5 “Sparrow”
Last month ARM announced a 2 GHz dual-core implementation of the Cortex-A9 that targets high-performance embedded apps. This month ARM is announcing a new processor core: the Cortex-A5 “Sparrow.”
Sparrow is intended for use in Internet-enabled consumer devices, particularly those with a user interface—such as cell phones, mobile audio devices, and digital picture frames. According to ARM, Sparrow is its smallest, most power-efficient Cortex core, and will initially target a 40LP process. The Cortex-A5 targets about 1 GHz in this process and is expected to consume 0.08 mW/MHz dynamic power for the core only. (Note that ARM quotes speed in a worst-case process, but quotes power in a typical process.) The core is available with an optional NEON SIMD unit; the CPU plus NEON will consume about 0.42 mm².
ARM claims that, in the same manufacturing process, the Cortex-A5 (without NEON) delivers performance comparable to that of the ARM1176 with silicon area comparable to the ARM926—while offering much better energy efficiency than either. In fact, ARM says that once the Cortex-A5 is available, ARM will not be recommending the ARM11 or ARM9 for new designs. The company will instead recommend either the Cortex-A5 or Cortex-R4, depending on whether an MMU is required (the Cortex-A5 has one, the Cortex-R4 doesn’t).
Like other Cortex-A cores (the Cortex-A8 and -A9), the Cortex-A5 is based on the ARMv7 instruction set architecture. The new core has an eight-stage pipeline and includes dynamic branch prediction. With the exception of limited dual issue of branches, the Cortex-A5 does not support superscalar operation like the Cortex-A8 and A9. Like the Cortex-A9, the Cortex-A5 is available in a “MP” (multiprocessor) variant that supports up to four cache-coherent Sparrows. This variant includes a Snoop Control Unit for coherency and a second AXI port.
The Cortex-A5 includes an ARMv7 MMU (to support a full OS) and 64-bit unified AMBA 3 AXI bus. NEON and floating-point units are optional; ARM says that it has made these units available primarily for compatibility with the Cortex-A8 and -A9 but the Cortex-A5 NEON unit is significantly less powerful; its data path width is 32 bits rather than 64.
According to ARM, the Cortex-A5 will provide about 1.57 DMIPS/MHz compared to 2.0 for the Cortex-A8 and 2.5 for the Cortex-A9. According to ARM, the Cortex-A8 runs at about 10-15% higher clock speed and requires about 3X the area and power consumption of the Cortex-A5. That makes the Cortex-A5 a smaller, less powerful core that still supports a full OS and provides compatibility with the more powerful Cortex cores—an interesting combination. Perhaps ARM is hoping to leverage the momentum of the Cortex-A8 in lower-performance applications.