Inside the LSI Logic ZSP500

A BDTI Technical Evaluation

The ZSP500 is a superscalar DSP core available for license from LSI Logic. The ZSP500 targets cost- and power-sensitive applications including cellular base stations and cellular handsets, voice over network (VoN) applications, and consumer devices such as personal digital assistants. Like its predecessor, the ZSP400, the ZSP500 features two 16-bit MAC units. However, the ZSP500 is considerably faster than the ZSP400—and is faster than many other dual-MAC DSP architectures.

This report provides a comprehensive qualitative analysis of the processors' architecture and features, along with a complete quantitative analysis based on results from BDTI's DSP benchmark suite. The performance of the ZSP500 is compared to that of key competitors, with benchmark results analyzed in terms of underlying architectural strengths and weaknesses.

This report will be of value to systems and chip designers, hardware and software engineers, processor designers, engineering managers, and product marketing managers.

Like all of the reports in the Inside series, Inside the LSI Logic ZSP500:

• Is based on hands-on programming experience
• Includes industry-standard BDTI Benchmark™ results
• Identifies processor strengths and weaknesses
• Compares performance to that of key competitors
• Provides timely information from the established leader in DSP technology analysis

Report includes analysis of the ZSP500:

Table of Contents

1. Introduction
2. About the authors
3. Selecting and using processor cores
4. Qualitative analysis of the ZSP500
5. Overview of competitors
   • 3DSP SP-5
   • ADI/Intel Micro Signal Architecture
   • LSI Logic ZSP400
   • TI TMS320C55xx
6. Analysis and comparison of benchmark results
7. Conclusions
8. Appendix: Complete BDTI Benchmark results for the ZSP500 and competitors

Excerpts from BDTI's analysis

The ZSP500 is a remarkably flexible architecture; for example, most ALU operations can execute on any of three ALUs, and can use any data registers as operands. In addition, most ZSP500 operations support both 16- and 32-bit data, which gives the ZSP500 better support for 32-bit precision than most DSP processors.

The ZSP500 two-cycle multiplier latency can often be hidden through the use of software pipelining, a programming technique that involves rearranging interdependent instructions. Unfortunately, software pipelining increases ZSP500 code size compared with that of processors with single-cycle multiplier latencies, such as the MSA1 and the TMS320C55xx.

Sample benchmark results

BDTI's 256-Point FFT Benchmark - Execution Time in microseconds
(lower is faster)

Inside the LSI Logic ZSP500 includes over 90 pages of benchmark data, in tables and graphs, showing results on each of the 12 BDTI Benchmarks for the ZSP500 and competitors.

Summary Report

A summary of the full Inside report is available for download. This Summary Report contains four pages of extensive excerpts from BDTI's analysis, including discussion of the ZSP500 core and benchmark results. Sample benchmark results are also included.

BDTI's Inside Series

Inside the LSI Logic ZSP500 is one of the many volumes in BDTI's series of focused technical analyses of single processors. The series also includes:

The BDTI Benchmarks™

The analysis in Inside the LSI Logic ZSP500 is based on the results of the BDTI Benchmarks, an industry-standard suite of DSP algorithm kernels. Each benchmark is painstakingly written and optimized in native assembly language following a strict specification.

Pricing, Shipping, and Ordering Information

First copy: $1,500
Additional copies: $650 each
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To order Inside the LSI Logic ZSP500, download an order form in HTML or PDF, complete and return it to BDTI by mail or fax.

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