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Inside the 3DSP SP-5

A BDTI Technical Evaluation

The first independent, in-depth report to evaluate the 3DSP SP-5, a fixed-point superscalar DSP processor core with SIMD (single instruction, multiple data) capabilities. This report provides a comprehensive qualitative analysis of the processor's architecture and features, along with a complete quantitative analysis based on results from BDTI's DSP benchmark suite.

The performance of the SP-5 is compared to that of key competitors, with benchmark results analyzed in terms of underlying architectural strengths and weaknesses.

This report will be of value to systems and chip designers, hardware and software engineers, processor designers, engineering managers, and product marketing managers.

Like all reports in the Inside series, Inside the 3DSP SP-5:

  • Is based on hands-on programming experience
  • Includes industry-standard BDTI Benchmark™ results
  • Identifies processor strengths and weaknesses
  • Compares performance to that of key competitors
  • Provides timely information from the established leader in DSP technology analysis

Report includes analysis of the SP-5's:

  • Architecture
  • Data path
  • Memory system
  • Addressing
  • Pipeline
  • Instruction set
  • Execution control
  • Peripherals
  • On-chip debugging support
  • Power consumption and management
  • Cost
  • Fabrication details
  • Development tools
  • Applications support
  • Advantages
  • Disadvantages

Table of Contents

  1. Introduction
  2. About the Authors
  3. Selecting and Using Processor Cores
  4. The 3DSP SP-5 Processor Core: Analysis
  5. Competitors
    • ADI/Intel Micro Signal Architecture
    • Infineon Carmel 10xx
    • LSI Logic LSI4xxx
    • StarCore SC140
  6. Benchmark Analysis
  7. Conclusion
  8. Appendix: BDTI Benchmark™ Results for the SP-5 and competitors

Excerpts from BDTI's analysis:

A disadvantage of superscalar instruction execution is that code execution times can be difficult to predict. Because instructions are dynamically scheduled for parallel execution at run-time, the pairing of instructions can change based on the current state of the pipeline. Branching, loops, and conditionally executed instructions complicate scheduling and add data dependency to instruction groupings. In real-time applications, this can lead to performance degradation that is difficult to understand and correct. When execution time is critical, the occurrence of pipeline stalls can be reduced by studying the simulator output, which provides detailed information on hazard conditions.

Overall, the SP-5 data path is very powerful and flexible. With two independent multipliers, four accumulators, two adders, multiple data widths, packed (SIMD) arithmetic, and superscalar execution, the SP-5 provides generous throughput for a wide variety of applications. The cores support of different data widths is more extensive than that of most DSPs; the support for 24-bit operands and complex data types is particularly unusual.

BDTI's qualitative analysis includes numerous similar insights into the SP-5, information invaluable to anyone interested in adopting the SP-5.

Sample benchmark results

BDTI's FFT Benchmark - Execution Time in microseconds
(lower is faster)


Inside the 3DSP SP-5 includes 100 pages of benchmark data, in tables and graphs, showing results on each of the 12 BDTI Benchmarks for the SP-5 and competitors.

BDTI's Inside Series

Inside the 3DSP SP-5 is one of many reports in BDTI's series of focused technical analyses of single processors. The series also includes:

Inside the CEVA CEVA-X1620 and CEVA-X1640
Inside the Intel PXA27x
Inside the StarCore SC1200 and 1400
Inside the LSI Logic ZSP500
Inside the Hitachi/STMicroelectronics SH4/ST40 and SH5/ST50
Inside the ARM ARM7, ARM9, and ARM9E
Inside the 3DSP SP5
Inside the Hitachi SH-DSP and SH3-DSP
Inside the Analog Devices/Intel MSA

The BDTI Benchmarks™

The analysis in Inside the 3DSP SP-5 is based on the results of the BDTI Benchmarks, an industry-standard suite of DSP algorithm kernels. Each benchmark is painstakingly written and optimized in native assembly language following a strict specification. This approach, applied by BDTI to a vast range of processors, allows for a fair and evenhanded evaluation of the capabilities of processor architectures.

For more information on BDTI's processor benchmarking methodology, read BDTI's white paper on the subject, Evaluating DSP Processor Performance, or contact BDTI at info@bdti.com.

Pricing, Shipping, and Ordering Information

First copy: $1,500
Additional copies: $650 each
Discounts are available on volume orders. Contact BDTI at info@bdti.com for details.
California orders must add appropriate sales tax.
All sales are final and are subject to BDTI's Terms and Conditions of Sale.

Reports are shipped via FedEx 2-Day service. International shipments are sent via FedEx International Priority Service. No charge for shipping within the U.S. International shipping is $75.
International customers must complete and return an Export Restriction Acknowledgement.

Orders may be placed with payment by check, purchase order, or credit card.
To order Inside the 3DSP SP-5, download an order form in HTML or PDF, complete and return it to BDTI by mail or fax.

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