Inside Reports
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Inside the
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The SC1200 and SC1400 are 16-bit fixed-point synthesizable DSP cores available for license from StarCore LLC. The SC1400 core architecture is based on the original SC140 core introduced by StarCore in April 1999. The SC1200 is a scaled-down version of the SC1400, containing two multiply-accumulate units instead of four as found in the SC1400. In other respects, the SC1200 and SC1400 are quite similar, and the two processors use the same instruction set.
The SC1400 targets a wide range of telecommunication applications, including 3G wireless and network infrastructure. The SC1200 targets applications that demand moderate performance and require lower cost or lower power consumption, such as 2G and 2.5G cellular telephones.
This report provides a comprehensive qualitative analysis of the processors' architecture and features, along with complete results from implementation of BDTI's DSP benchmark suite. Tables and graphs provide clear comparison of the performance of the SC1200 and SC1400 with that of key competitors.
This report will be of value to system and chip designers, hardware and software engineers, engineering managers, and product marketing managers.
Like all of the reports in the Inside series, Inside the StarCore SC1200 and SC1400:
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The SC140 architecture continues to be used in chips from Motorola. When it was introduced in 1999, the SC140 was the first mainstream VLIW-based DSP processor that combined low power consumption with very high performance.Several years have passed, however, and vendors such as Texas Instruments and Analog Devices have had plenty of time to develop new DSPs and improve existing architectures.The original SC140 architecture, reincarnated as the SC1400, now faces stiffer competition from the latest high-performance cores and packaged processors, especially for infrastructure applications where power consumption is less important.
Having a common register set for all data paths eases programming. Because instruction latencies are low and a register can be used as both source and destination in the same instruction cycle, sixteen registers should be sufficient to support the processor's execution units. The register width, 40 bits, is sufficient to provide the necessary dynamic range for applications that use 16-bit data.
BDTI's Real Block FIR Benchmark
Execution Time in microseconds
(lower is faster)
Inside the StarCore SC1200 and SC1400 includes over 90 pages of benchmark data, in tables and graphs, showing results on each of the 12 BDTI Benchmarks for the SC1200, SC1400, and competitors.
Inside the StarCore SC1200 and SC1400 is the one of the many volumes in BDTI's series of focused technical analyses of single processors. The series currently includes the following reports:
The benchmark results in Inside the StarCore SC1200 and SC1400 are derived from the application of the BDTI Benchmarks, an industry-standard suite of DSP algorithm kernels. Each benchmark is painstakingly written and optimized in native assembly language following a strict specification.
First copy: $1,500
Additional copies: $650 each
Discounts are available on volume orders.Contact BDTI at info@bdti.com for details.
California orders must add appropriate sales tax.
All sales are final and are subject to BDTI's Terms and Conditions of Sale.
Reports are shipped via FedEx 2-Day service.International shipments are sent via FedEx International Priority Service.No charge for shipping within the U.S.International shipping is $75.
International customers must complete and return an Export Restriction Acknowledgement.
Orders may be placed with payment by check, purchase order, or credit card.
To order Inside the StarCore SC1200 and SC1400, download an order form in HTML or PDF, complete and return it to BDTI by mail or fax.
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