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3Soft M320C50 DSP Core
The M320C50 is a licensable 16-bit fixed-point DSP core from 3Soft
Corporation, a subsidiary of Mentor Graphics. Since the M320C50 is a
core, it is not sold off-the-shelf in chip form. Rather, it is
intended to be used as the basis of an application-specific integrated
circuit (ASIC). The first M320C50-based chip was fabricated in
1995. The M320C50 can be implemented with either a 5.0-volt or
3.0-volt power supply; with a 5.0-volt supply, it is capable of
executing at up to 50 MIPS.
The M320C50 is designed to be compatible with the Texas Instruments
TMS320C5x processor in architecture, instruction set, and instruction
execution times. According to 3Soft, the M320C50 provides a complement
of peripherals that are identical to those found on the Texas
Instruments TMS320C50 processor. These include a general-purpose
synchronous serial port, a TDM-capable synchronous serial port, and a
16-bit timer. Since 3Soft provides Verilog HDL and VHDL models for
these peripherals, the ASIC designer can modify or remove them as
required by the application.
As in the TMS320C5x family, the M320C50 data path consists of a
16x16->32-bit multiplier, a 32-bit ALU, two barrel shifters, a
32-bit accumulator, and a 32-bit ``accumulator buffer'' that can be
exchanged with the accumulator. Separate from the main data path, the
processor also includes a ``parallel logic unit'' that can perform
logic operations directly on operands in memory.
The M320C50 provides a 64-Kword program memory space and a 64-Kword
data memory space. Like the TMS320C5x, the M320C50 supports one
program access and one data access per instruction cycle.
The M320C50 does not contain its own on-core memory; it provides
several buses designed solely for connections to on-chip memory. The
ASIC designer can configure an M320C50-based ASIC to use up to 32
Kwords of on-chip program RAM or ROM and up to 32 Kwords of on-chip
data RAM or ROM. As on the TMS320C5x, the M320C50 supports both
single- and dual-access memory. Single-access memory can be placed in
either data or program space and can optionally be shared between the
two spaces, while dual-access memory is restricted to data memory. The
ASIC designer can specify the size of the blocks that make up the
single-access RAM regions of the M320C50 memory. (The M320C50 supports
one access to a given block of single-access RAM every instruction
cycle). Dual-access RAM blocks must be either 512x16 or 32x16 in size;
a maximum of two 512x16 and one 32x16 block is allowed.
To maintain compatibility with the TMS320C5x family, the M320C50
provides an additional memory interface that is identical to the
TMS320C5x external memory interface. This interface is intended for
connection to off-core memory or peripherals.
M320C50 addressing modes are compatible with the TMS320C5x, and
include paged memory-direct, register-direct, and register-indirect
addressing. Immediate data is also supported. Bit -reversed addressing
can be accomplished by using reverse-carry arithmetic.
For a complete evaluation of this processor, contact BDTI.
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