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3Soft M320C25 DSP Core
The M320C25 core, introduced in 1993, is a licensable 16-bit
fixed-point DSP core from 3Soft Corporation, a subsidiary of Mentor
Graphics. Since the M320C25 is a core, it is not sold off-the-shelf in
chip form. Rather, it is intended to be used as the basis of an
application-specific integrated circuit (ASIC). According to the
vendor, licensees have successfully operated the M320C25 core at both
5.0 and 3.3 volts, and have achieved 15 MIPS performance.
Most DSP cores do not provide peripherals, instead allowing the ASIC
designer to choose surrounding peripherals that are specific to the
target application. The M320C25, however, does include a synchronous
serial port and a timer.
The architecture of the M320C25 is similar to that of the Texas
Instruments TMS320C25, and the two families have nearly identical
instruction sets.
The M320C25 data path is comprised of a 16x16->32-bit single-cycle
multiplier, a 32-bit ALU, and a single 32-bit accumulator. No guard
bits are available in the accumulator.
The M320C25 uses separate program and data memory spaces. Each memory
space has its own 16-bit address and data buses. On-chip memory is
optional but can provide higher-bandwidth memory access than off-chip
memory. The on-chip program RAM or ROM can be up to 4Kx16, and is
connected to the program address and data buses. On-chip data RAM
consists of up to two blocks, one of which can be up to 256x16 in size
and the other of which can be up to 32x16 in size. These blocks are
connected to the data bus set. On-chip data/program RAM is a single
block of up to 256x16 in size. This RAM is connected to both program
and data buses, and can be configured as either program or data
memory.
In normal operation, one instruction is fetched from program memory
and one operand from data memory every instruction cycle. This implies
that instructions requiring two data fetches (such as
multiply-accumulate) execute in two instruction cycles. However, the
M320C25 has a single-instruction repeat buffer which allows such
instructions to execute in one cycle under certain circumstances.
The M320C25 supports both external program and data memory. External
program and data addresses and are multiplexed together on a 16-bit
external address bus; similarly, external program and data memory data
buses are also multiplexed together on a 16-bit external data bus. The
core can run at full speed when executing from external program memory
(assuming zero wait states), but requires additional cycles to access
external data memory, even when executing from internal program
memory. Externally generated wait states are supported via a READY
pin. Programmable wait states are not supported.
The M320C25 provides register-direct, paged memory-direct, and
register-indirect addressing. Bit-reversed addressing is supported
through reverse carry propagation. Immediate data is also supported.
For a complete evaluation of this processor, contact BDTI.
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