Floating-Point DSP Processors
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Floating-Point DSP Processors |
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Analog Devices ADSP-TS0xx "TigerSHARC"The ADSP-TS0xx is a family of DSP processors from Analog Devices based on the "TigerSHARC" core, introduced in October of 1998. The ADSP-TS0xx is a VLIW architecture, and can issue and excute up to four 32-bit instructions per clock cycle. The ADSP-TS0xx operates on a variety of data widths, and supports both fixed- and floating-point formats. Although the ADSP-TS0xx has some elements in common with the ADSP-2116x, the ADSP-TS0xx is neither source- nor object-code compatible with previous Analog Devices processors, and its overall architecture is significantly different. The ADSP-TS0xx family targets high-performance applications such as those found in the telecommunications industry (wireless base stations, VoN/VoIP concentrators, cable modems, xDSL, encryption, and third-generation ("3G" wireless), and high-performance signal processing markets (graphics, CAT scan, MRI, ultrasound, radar, sonar), especially applications that require multiprocessing. The first ADSP-TS0xx family member, the ADSP-TS001, is expected to begin sampling at 120 MHz with a core voltage of 1.8 volts in late 2000. Like Analog Devices' ADSP-2116x, the ADSP-TS0xx provides two identical fixed/floating-point data paths, each containing three distinct arithmetic units: an ALU, a MAC, and a shifter. The ADSP-TS0xx supports two types of SIMD operation. As with the ADSP-2116x, a single instruction can control both data paths, allowing the same operation to be executed on different operands in both data paths. In addition, a single instruction can cause an execution unit in a single data path to perform SIMD operations on multiple sets of input operands. These two types of SIMD operations can also be combined so that a single instruction causes the two data paths to perform identical SIMD operations. The ADSP-TS0xx supports six data types: 8-bit, 16-bit, 32-bit, and 64-bit fixed-point, 32-bit IEEE-754 floating-point, and 40-bit extended-precision floating-point. Instructions are included to convert between the various floating-point and fixed-point formats. The ALU, MAC, and shifter access a register file (one file per data path) that contains thirty-two 32-bit general-purpose registers. Each MAC provides four 32-bit dedicated accumulation registers and a 32-bit guard bit register for fixed-point multiply-accumulates. Using SIMD instructions in both data paths, the ADSP-TS0xx can, for example, perform up to eight 16x16->32-bit fixed-point multiplications per cycle. The ADSP-TS0xx also supports up to two 32x32->40-bit floating-point multiplications with single-cycle throughput. There is no floating-point multiply-accumulate instruction; floating-point multiplication products can be accumulated using separate ALU instructions. The data path shifter units perform single-bit manipulation, bit-field manipulation, and rotation, logical, or arithmetic shifting operations of up to 64 bits left or right. The ADSP-TS0xx memory system consists of on-chip 32-bit memory, up to approximately 4 Gwords of general-purpose off-chip 32-bit memory, and up to 3.5 Mwords of off-chip multiprocessor memory (i.e., the 32-bit internal memory of up to seven other ADSP-TS0xx chips). On-chip memory consists of three blocks of up to 512K 32-bit words, each arranged in a unified, 32-bit word-addressable space that contains both instructions and data. The ADSP-TS0xx contains three 128-bit internal data and instruction buses, each of which is connected to one of the on-chip memory blocks. Up to 128 bits can be fetched from each of the three on-chip memories in each instruction cycle. When executing instructions from on-chip memory, the maximum data bandwidth for an ADSP-TS0xx operating at 120 MHz is 1.92 billion 16-bit words/second (sixteen 16-bit words/cycle). The external 32-bit memory space is divided into six regions: multiprocessor memory, approximately 4 Gwords of "host memory" (nominally intended for memory that is shared with a host processor, but usable for other memory functions as well), boot EPROM, and three external memory banks of up to 67 million 32-bit words each, one of which supports a glueless interface to SDRAM. The external address bus is 32 bits wide, which allows the processor to access approximately 4 Gwords of multiprocessor or external memory. The external data bus width is configured to 32 bit or 64 bits separately for host memory, multiprocessor transactions, and other external memory. The external memory interface can perform accesses at a maximum rate of one 64-bit word per system clock cycle, compared with one 128-bit word per master clock cycle for on-chip memory. The ADSP-TS0xx has two address generation units, both of which contain a data path with an ALU, a shifter, and a memory-mapped register file of thirty-two 32-bit registers. Each address generation unit's data path supports 32-bit fixed-point integer operations, and may execute one instruction per instruction cycle. The ADSP-TS0xx supports register-direct, register-indirect with post-increment, indexed, modulo, and bit-reversed addressing, as well as immediate data. There is almost no hardware support for looping on the ADSP-TS0xx—no DO instruction, and no stack on which to store loop variables. There are, however, two special-purpose loop counters that allow up to 2^32 repetitions each of up to two nested loops. The ADSP-TS001 on-chip peripherals include two timers (with a 64-bit count for each), four 8-bit link ports, a 14-channel DMA controller, and four bit-I/O pins. The external memory interface also functions as a host port. As of June 2000, quantity 10,000 prices for ADSP-TS001 family members were projected to be $150.00. A complete analysis of this processor is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition .
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