Fixed-Point DSP Processors
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Fixed-Point DSP Processors |
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Texas Instruments TMS320C62xxThe TMS320C62xx is the latest family of fixed-point DSP processors from Texas Instruments. It is based on a VLIW-like architecture which allows it to execute up to eight RISC-like instructions per clock cycle. The first member of the TMS320C62xx family, the TMS320C6201, is available at 200 MHz. It uses an 1.8-volt core supply (with 3.3-volt I/O), and executes up to 400 million MACs per second. (Since TMS320C62xx instructions often perform fewer operations than typical instructions on other DSPs, a MIPS comparison between the TMS320C62xx and other DSPs is not meaningful. Therefore, instead of MIPS, we use the number of MACs per second as a shorthand performance metric.) As of September 1999, two other family members, the TMS320C6202 and the TMS320C6211, are sampling at 250 MHz and 150 MHz, respectively. Texas Instruments also offers the TMS320C67xx family, which extends the TMS320C62xx architecture with support for floating-point arithmetic and 64-bit data. The TMS320C62xx has two nearly identical data paths. Each data path includes a set of four execution units, a general-purpose register file, and paths for moving data between memory and the registers. The four execution units in each data path comprise two ALUs, a 16x16->32-bit multiplier, and an adder/subtractor which is used for address generation. All eight execution units can operate in parallel. The two register files each contain sixteen 32-bit general-purpose registers. These registers can be used for storing addresses or data. To support 40-bit arithmetic, pairs of adjacent registers can be used to hold 40-bit data. Two of the four units in each data path can operate on 40-bit operands, which corresponds to having a 32-bit register with eight guard bits. The TMS320C62xx provides support for barrel shifting, bit field extraction, exponent detection, and normalization. The on-chip memory system of the TMS320C62xx implements a modified Harvard architecture, providing separate address spaces for program and data memory. Program memory has a 32-bit address bus and a 256-bit data bus. Data memory has two 32-bit address buses and two 32-bit data buses. The only member of the TMS320C62xx family that is currently available, the TMS320C6201, has 64 Kbytes of 32-bit on-chip program RAM and 64 Kbytes of 16-bit on-chip data RAM. The maximum sustainable on-chip data memory bandwidth for the 200 MHz TMS320C6201 is four hundred 32-bit Mwords or eight hundred 16-bit Mwords per second. The TMS320C6201 has one external memory interface, which provides a 23-bit address bus and a 32-bit data bus. These buses are multiplexed between program and data memory accesses. The peak external memory bandwidth for a 200 MHz TMS320C6201 is 200 32-bit Mwords per second. In typical applications, however, the external memory bandwidth is expected to be significantly lower because peak bandwidth requires very fast SRAM, which is not practical in many applications. Addressing modes supported by the TMS320C62xx include register-direct, register-indirect, indexed register-indirect, and modulo addressing. Immediate data is also supported. The TMS320C62xx does not support hardware looping, and hence all loops must be implemented in software. However, the parallel architecture of the processor allows the implementation of software loops with virtually no overhead. The peripherals on the TMS320C6201 include a host port, four-channel DMA controller, two TDM-capable buffered serial ports and two 32-bit timers. As of October 1998, quantity 10,000 prices for TMS320C62xx family members range from $90.00 to $121.00. A complete analysis of the TMS320C62xx, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition.
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