Texas Instruments TMS320C54x

The Texas Instruments TMS320C54x is a family of 16-bit fixed-point DSPs. TMS320C54x processors target high-volume, low-power applications. The first family members were introduced in Japan in 1994 and in the U.S. in 1995. The fastest processor in the family runs at 160 MHz with a 1.6-volt core supply voltage. The lowest-voltage family member runs at 120 MHz and 1.5 volts. The TMS320C54x family also includes multi-core devices not covered in this overview.

Architecture

The TMS320C54x data path is based on five execution units: a multiply-accumulate unit, a 40-bit ALU, a barrel shifter, an exponent detector, a compare-select-store unit (CSSU), and two 40-bit accumulators (A and B).

The TMS320C54x multiply-accumulate (MAC) unit performs a 16 × 16 → 32-bit fractional multiply-accumulate operation in a single instruction cycle. The multiplier supports signed/signed multiplication, signed/unsigned multiplication, and unsigned/unsigned multiplication. These operations allow efficient extended-precision arithmetic. Many instructions using the MAC unit can optionally specify automatic round-to-nearest rounding.

The ALU supports common logical and arithmetic operations. The ALU also supports dual 16-bit operations using SIMD arithmetic. In this mode, the lower 32 bits of the ALU act as two parallel 16-bit ALUs. Among other things, this capability is useful in conjunction with the compare-select-store unit for implementing a Viterbi decoder.

The 40-bit barrel shifter can perform arithmetic and logical shifts by up to 31 bits left or by up to 16 bits right in a single instruction cycle. Shifter inputs can come directly from data memory or from either of the two accumulators. Shifter outputs can be sent to the ALU or stored in memory.

The TMS320C54x divides memory into word-addressable program and data spaces. Each space can contain 64 Kwords of instructions or data. Members of the TMS320C54x family differ in the size and organization of their on-chip memory.

The processor accesses on-chip memory over four sets of address and data buses: one set of program buses, two sets of data read buses, and one set of data write buses. The program bus set is connected to program/data ROM and RAM. The data bus sets are connected to several blocks of dual-access program/data RAM (DARAM) that support two reads or one read and one write operation per instruction cycle. DARAM can be mapped into either program space or both program and data spaces under software control on all TMS320C54x variants. Most TMS320C54x family members also contain single-access RAM (SARAM) that can be mapped into either data space or program space. Additionally, all TMS320C54x family members feature on-chip program ROM. At the maximum master clock speed of 160 MHz, the on-chip peak and maximum sustainable data memory bandwidth is 320 million 16-bit words/second for reads, or a combination of 160 million 16-bit words/second for reads and 160 million 16-bit words/second for writes.

Addressing modes include register-direct, paged memory-direct, stack-pointer-relative, memory-direct, and register-indirect. The TMS320C54x also supports immediate data. The TMS320C54x supports modulo addressing for use with circular buffering, and also provides bit-reversed addressing capabilities.

The TMS320C54x supports both single- and multi-instruction hardware loops. Single-instruction hardware loops are not interruptible; multi-instruction loops are interruptible. Loops can be executed from 1 to 65,536 times.

Peripherals

In addition, Texas Instruments provides a variety of memory, peripheral and support blocks that can be integrated with a TMS320C54x core in an ASIC. Blocks include configurable SRAM and ROM, and full or partial implementations of a variety of mass-storage application specific support blocks, e.g., ATA interface blocks and SCSI blocks. Contact Texas Instruments for further information.

Power Consumption

The TMS320C54x provides three low-power modes invoked by the IDLE1, IDLE2, and IDLE3 instructions. In all idle modes, the clock is turned off to the processor’s core, reducing power consumption. In IDLE1 mode, on-chip peripherals (the serial port and timer) and interrupt lines remain active, and any unmasked interrupt wakes the processor. In IDLE2 mode, the on-chip peripherals are turned off, and only an interrupt on an external interrupt line wakes the processor. IDLE3 mode is similar to IDLE2 mode but it also turns off the on-chip crystal oscillator and PLL circuitry. As an additional power management feature, the output clock and the internal clock to the external interfaces can be turned off if they are not needed.

Cost

For Additional Information

Last updated January 2005.