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Texas Instruments TMS320C2xx Family and T320C2xLP Core

The TMS320C2xx is a family of 16-bit fixed-point processors based on the T320C2xLP DSP core. The TMS320C2xx family was introduced in 1995, and represents a cross between Texas Instruments' earlier TMS320C2x and TMS320C5x families. The TMS320C2xx is generally compatible at the assembly-language level with the TMS320C2x; however, some instructions have been changed, and others have been added. TMS320C2xx processors target high-volume, cost-sensitive applications such as set-top boxes, telephones, hard disk drives, and modems. The newest family member, the TMS320F240, is aimed at motor control solutions. For sufficiently high volumes, Texas Instruments can also build customer-designed ASICs based on the T320C2xLP core. As of October 1998, the fastest members of the family run at 40 MIPS with a 5.0-volt supply.

The data path of the T320C2xLP core and TMS320C2xx processors centers on a 16x16->32-bit single-cycle multiplier, a 32-bit ALU, a restricted input barrel shifter, a restricted output barrel shifter, and a single 32-bit accumulator. No guard bits are available in the accumulator. To prevent overflow, the output of the product register may be right-shifted by six bits before being presented to the ALU for accumulation. This allows up to 128 multiply-accumulate operations before overflow becomes a possibility. Accumulator saturation on overflow can be enabled via a special instruction.

The multiplier supports signed/signed or unsigned/unsigned multiplications. The multiplier performs integer multiplication by default, but the processor can be configured to shift the product one bit left, thus allowing fractional multiplication. The TMS320C2xx does not have explicit hardware support for exponent detection and normalization, but an instruction that performs iterative exponent detection and normalization on the accumulator is provided.

ALU operations are performed with single-cycle throughput. The TMS320C2xx cannot perform an instruction fetch and two data reads simultaneously; thus, although a multiply-accumulate instruction is provided, a multiply-accumulate operation has a throughput of two instruction cycles unless it is executed from the processor's single-instruction repeat buffer.

The T320C2xLP core and TMS320C2xx processors use separate program and data memory spaces. Each memory space can contain up to 64 Kwords of word-addressable 16-bit memory. The T320C2xLP core contains three separate sets of on-core 16-bit address and data buses: the program bus set, the data read bus set, and the data write bus set.

The T320C2xLP includes 544x16 bits of dual-access RAM (DARAM) on-core. The DARAM supports one read and one write operation (but not two read or two write operations) per instruction cycle. Because the DARAM memory is on-core, all TMS320C2xx processors include the 544x16 on-chip DARAM. The size and configuration of additional on-chip memory varies with the family member; some variants include additional RAM and flash EEPROM. Coupled with appropriate types of memory, the buses allow the processor to achieve one program fetch, one data read, and one data write per instruction cycle, resulting in a combined data memory bandwidth of eighty 16-bit Mwords/second on a 40 MIPS TMS320C203 (when reads and writes are performed simultaneously).

The T320C2xLP core provides two separate external interfaces. The first, called the "memory interface," is specifically intended for connection to the on-chip memory blocks. The second, the "logic interface," presents a multiplexed external interface intended for connection to off-core peripherals and custom circuitry. The logic interface can achieve one external read every instruction cycle, assuming zero wait states. Writes over the logic interface take at least two instruction cycles. The TMS3200C2xx external memory interface pins match the logic interface of the T320C2xLP, except for the addition of a wait-state generator. The maximum off-chip memory bandwidth is thus forty 16-bit Mwords/second for reads or twenty 16-bit Mwords/second for writes on a 40 MIPS TMS320C203.

The T320C2xLP core and TMS320C2xx processors provide register-direct, paged memory-direct, and register-indirect addressing, and support for immediate data. The TMS320C2xx supports bit-reversed addressing through reverse carry propagation; modulo addressing is not supported.

Like the TMS320C2x, the T320C2xLP core and TMS320C2xx processors support single-instruction hardware loops. Multi-instruction hardware loops are not supported.

The T320C2xLP core does not contain any on-core peripherals. Instead, the designer of an ASIC containing the T320C2xLP core must add peripherals appropriate to the design at hand. TMS320C2xx processors feature various peripherals, ranging from only a timer on the TMS320C209 to a variety of peripherals on the TMS320F240, including D/A and A/D converters, pulse-width modulation outputs, etc. The TMS320F240 peripherals are primarily intended for motor control applications. A 16-bit timer is found on all TMS320C2xx processors except the TMS320F240.

As of October 1998, quantity 10,000 prices for TMS320C2xx family members range from $5.00 to $16.00. A complete analysis of this processor, including BDTI Benchmark™ results, is available in BDTI's technical report, Buyer's Guide to DSP Processors, 1999 Edition. An updated analysis, without BDTI Benchmark™ results, is available in Buyer's Guide to DSP Processors, 2001 Edition..

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