Fixed-Point DSP Processors
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Fixed-Point DSP Processors |
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Texas Instruments TMS320C5xThe TMS320C5x is Texas Instruments' third generation of 16-bit fixed-point DSPs. The TMS320C5x architecture is similar to (and assembly source-code compatible with) the earlier TMS320C2x family, but architectural and fabrication enhancements allow it to more than quadruple the TMS320C2x's performance. The TMS320C50, the first member of the family, was introduced in 1989. More recent additions to the family include low-power members (TMS320LC5x) operating with a 3.3-volt supply. The fastest family members available as of October 1998 achieve an execution rate of 50 MIPS at either 5.0 volts or 3.3 volts. TMS320C5x processors are targeted at high-performance applications such as digital cellular telephones, speech coding, and high-speed modems. The TMS320C5x is also available as a core for use in ASICs designed by customers and fabricated by Texas Instruments. The core is designated the TMS320C52C, and, like the TMS320C52 processor, includes one Kword of RAM and four Kwords of ROM on-core. According to Texas Instruments, the TMS320C52 core can operate at speeds of up to 50 MIPS at 5.0 volts and 25 MIPS at 3.3 volts. The TMS320C5x data path evolved from that of the TMS320C2x. The key units in the data path are a 16x16->32-bit multiplier, a 32-bit ALU, a 32-bit accumulator, a 32-bit secondary accumulator (which can be used for temporary storage), and several barrel shifters. The multiplier is capable of single-cycle execution and supports signed/signed or unsigned/unsigned multiplications. The processor supports fractional multiplication via left-shifting the multiplier output value by one. No guard bits are available in the accumulator. To prevent overflow, the output of the product register may be right-shifted by six bits before being presented to the ALU for accumulation. This allows up to 128 multiply-accumulate operations before overflow becomes a possibility. As with previous fixed-point parts from Texas Instruments, the accumulator can be optionally set to saturate on overflow by setting an appropriate mode bit. In addition to the fixed-point arithmetic data path, the TMS320C5x features a special logic unit, called the "parallel logic unit," that allows bit set, clear, test, and toggle operations on control/status registers and memory locations. Because it is separate from the fixed-point data path and accumulator, its use does not require saving and restoring the contents of the accumulator. The on-chip memory system of the TMS320C5x implements a modified Harvard architecture providing separate 16-bit bus sets for program and data memory spaces. TMS320C5x processors provide two kinds of on-chip RAM: single-access RAM and dual-access RAM. Each block of single-access RAM supports either one read or one write per instruction cycle. In contrast, each block of dual-access RAM supports one read and one write per instruction cycle. All TMS320C5x processors include one 32x16 block and one 512x16 block of dual-access RAM mapped into data memory, and one 512x16 block of dual-access RAM that can be mapped into either program or data memory (but not both simultaneously) under software control. Additionally, all TMS320C5x processors except the TMS320C52 include a varying number of blocks of single-access RAM that can be mapped into program or data memory (or both simultaneously). TMS320C5x processors also contain varying amounts of program ROM. The TMS320C5x has a maximum data access rate of two memory reads (one program/data word and one data word) or one memory write per instruction cycle. For a 50 MIPS TMS320C5x, this corresponds to a peak on-chip data memory bandwidth of one hundred 16-bit Mwords/second for reads. Maximum sustainable on-chip data memory bandwidth for both reads and writes is fifty 16-bit Mwords/second. TMS320C5x processors have a 16-bit external address bus and a 16-bit external data bus. The internal program and data buses are multiplexed on the two external buses. External reads take one cycle, assuming zero-wait-state external memory. External writes take two instruction cycles, unless they are immediately preceded or followed by an external read, in which case they take three instruction cycles (again, assuming zero-wait-state external memory). Thus, the maximum sustainable external memory bandwidth for a 50 MIPS TMS320C5x is fifty 16-bit Mwords/second for reads and twenty-five 16-bit Mwords/second for writes. The TMS320C5x provides support for register-direct, paged memory-direct, and register-indirect addressing. The TMS320C5x supports bit-reversed addressing through reverse-carry propagation. In addition, two circular buffers on the TMS320C5x can be active at any time. Immediate data is also supported. The TMS320C5x supports both single- and multiple-instruction hardware loops. TMS320C5x on-chip peripherals include a timer and at least one synchronous serial port. Most TMS320C5x family members have a second synchronous serial port that supports time-division multiplexed (TDM) operation. The TMS320LC57 and TMS320C57S also include a host port. As of October 1998, quantity 10,000 prices for TMS320C5x family members range from $11.00 to $35.00. A complete analysis of the TMS320C5x, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 1999 Edition.
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