Fixed-Point DSP Processors
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Fixed-Point DSP Processors |
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Texas Instruments TMS320C2xThe TMS320C2x family was introduced in 1985, and is the second generation of 16-bit fixed-point DSPs from Texas Instruments. As of March 1997, the fastest member of the TMS320C2x family, the TMS320C25-50, executes at 12.5 MIPS using a 5.0-volt supply. TMS320C2x family members have seen use in a wide variety of embedded systems including modems, speech compression, and telecommunications signaling. The architecture is similar to that of the TMS320C1x family, but features a number of improvements, including increased address spaces, larger on-chip memories, hardware loop support, and a multiply-accumulate instruction. The TMS320C2x has been largely superseded by the TMS320C2xx and other, newer fixed-point processor architectures from Texas Instruments, and Texas Instruments does not recommend the TMS320C2x for new designs. However, we include the TMS320C2x because of its historical importance and the abundance of software, tools, and documentation that is available for the TMS320C2x. The TMS320C2x data path includes a 16x16->32-bit single-cycle multiplier, a 32-bit ALU, and a single 32-bit accumulator. The multiplier performs signed/signed or unsigned/unsigned multiplication on integer or fractional operands. ALU operations are performed with single-cycle throughput. Both the full accumulator and the 16-bit lower half of the accumulator can be left-shifted from zero to seven bits before being written to the data bus. No guard bits are available in the accumulator. As with the TMS320C1x, accumulator saturation can be enabled via a special instruction. An overflow status bit is provided to indicate that overflow has occurred in the ALU. Unlike the TMS320C1x, the TMS320C2x ALU features a carry bit, permitting extended precision arithmetic and rotate-through-carry instructions. The TMS320C2x uses separate program and data memory spaces. Each memory space has its own 16-bit address and data buses on-chip. On-chip program ROM is connected to the program address and program data buses. Size and organization of on-chip ROM and RAM varies depending on the family member. Some family members can use their RAM for either program or data memory (but not both), while others have dedicated blocks of RAM used for data memory only. On-chip RAM that can be configured as either program or data memory is mapped to a portion of both the program memory space and the data memory space. Hence, if a block of RAM is configured as program memory, the corresponding portion of data memory is unavailable, and vice versa. In normal operation, one instruction is fetched from program memory and one operand from data memory every instruction cycle. This implies that, like the TMS320C1x, instructions requiring two data fetches (such as multiply-accumulates) execute in two instruction cycles. Likewise, instructions that occupy two words in memory also take at least two instruction cycles to execute. Thus, the maximum data bandwidth is 12.5 16-bit Mwords/second on a 12.5 MIPS TMS320C25. However, the TMS320C2x features a single-instruction repeat buffer that frees the program buses for data fetches when an instruction is being repeated. In this case, assuming operands are in internal memory, instructions requiring two data fetches can execute in one instruction cycle. Unlike the TMS320C1x, the TMS320C2x supports both external program and data memory. External program and data addresses are multiplexed together on a 16-bit external address bus; similarly, program and data memory data buses are also multiplexed together on a 16-bit external data bus. The processor can run at full speed when executing from external program memory (assuming zero wait states), yielding a maximum external memory bandwidth of 12.5 16-bit Mwords/second on a 12.5 MIPS TMS320C25. However, additional instruction cycles are required to access external data memory, even when executing from internal program memory. The TMS320C2x supports immediate data and register-direct, paged memory-direct, and register-indirect addressing modes. The TMS320C2x also supports bit-reversed addressing through reverse carry propagation. Circular addressing is not available. Unlike the TMS320C1x, the TMS320C2x provides support for hardware looping. Peripherals on all TMS320C2x processors comprise a synchronous serial port and a timer. As of March 1997, quantity 1,000 prices for TMS320C2x family members range from $12.40 for the 10 MIPS TMS320C25 in a 68-pin PLCC package to $70.53 for the 10 MIPS TMS320C25 in a 68-pin PGA. For a complete evaluation of this processor, including BDTI Benchmark ™ results, contact BDTI.
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