General-Purpose Processors
|
||
General-Purpose Processors |
|
|
| HOME << |
|
|
|
||
Hitachi SH-DSPThe SH-DSP is a hybrid 16-bit DSP/32-bit RISC microcontroller architecture from Hitachi, targeted at low-cost embedded applications. Samples of the SH-DSP first became available in the third quarter of 1996, running at 60 MIPS with a 60 MHz clock and a 3.0- or 3.3-volt power supply; the product was formally announced in March 1997. Volume production is expected to begin in September 1997, according to Hitachi. The SH-DSP is compatible with Hitachi's SH-2 microcontroller, which is reported to be the world's best-selling 32-bit RISC processor. The SH-DSP augments the SH-2 microcontroller architecture with a substantial array of fixed-point DSP-oriented instructions and features. These additions give the SH-DSP capabilities comparable to those of typical 16-bit DSPs. The SH-DSP is a single processor and processes a single instruction stream. The SH-DSP hybrid microcontroller/DSP architecture represents a unique approach—integration of extensive DSP capabilities into an existing general-purpose architecture. Hitachi's approach is an interesting counterpoint to that taken by Motorola with the DSP568xx—a new 16-bit DSP architecture with many microcontroller features. The SH-DSP's program control unit and microcontroller data path are used to execute microcontroller instructions. DSP instructions make use of the processor's DSP unit (containing a 16-bit fixed-point DSP data path), the data address generator, the microcontroller data path (which, along with the data address generator is used for address generation), and the program control unit. The SH-DSP DSP unit uses a 16-bit fixed-point architecture. The DSP data path contains a 40-bit ALU providing eight guard bits, a 16x16->32-bit multiplier, a barrel shifter, an exponent detector, two 40-bit accumulators, and six 32-bit operand registers. The SH-DSP DSP-unit data path closely resembles the data paths of typical 16-bit fixed-point DSPs. The microcontroller data path contains sixteen 32-bit registers. These registers include 15 general-purpose registers (R0-R14) and the stack pointer (R15) that are defined as part of the SH-2 architecture. Some of these registers are used as address registers by the DSP unit. Data can be transferred between general-purpose registers and most DSP-unit registers in a single cycle via microcontroller instructions. The SH-DSP provides a single memory space populated by up to five types of memory: four on-chip banks (X ROM, X RAM, Y ROM, and Y RAM) and off-chip memory. The SH-DSP provides three sets of buses: I, X, and Y. The I bus set consists of a 32-bit address bus and a 32-bit data bus. It is used for accessing instructions, which can reside in any on-chip memory bank or in off-chip memory. The I bus set is also used for accessing data for microcontroller operations. The X and Y bus sets each consists of a 16-bit address bus and a 16-bit data bus, and are used only for accessing data in the X and Y memory banks, respectively. For DSP-unit operations, the processor can fetch an instruction and complete two 16-bit data memory accesses (parallel moves) in a single instruction cycle assuming no memory bank conflicts. The first production version of the SH-DSP contains 1Kx32 of X RAM, 6Kx32 of X ROM, 1Kx32 of Y RAM, and 6Kx32 of Y ROM on-chip, according to Hitachi. This memory can be accessed as 32-bit words (for DSP-unit instructions, microcontroller data, or DSP-unit double-precision data) or as 16-bit words (for DSP-unit data or microcontroller instructions). Of the three on-chip bus sets, only the I bus set can be used to access off-chip memory. The external memory interface consists of a 24-bit address bus and a 32-bit data bus along with four chip-select lines. Each chip-select line is used for one of four 16Mx32 segments of external memory. This allows the processor to access up to 64Mx32 of off-chip memory. The maximum bandwidth of the external memory interface is one 32-bit word per bus cycle. Both programmable and externally requested wait states are available. In addition, segments two and three of external memory can be configured for direct connection to DRAM. In this configuration, the external memory interface provides all necessary control and refresh signals for interfacing with DRAM devices. Signaling for page-mode DRAMs is also provided. Similarly, specific segments of external memory can be configured for interfacing to burst-ROM or pseudo-SRAM devices. The SH-DSP does not provide support for virtual memory. The price for the 60 MIPS SH-DSP is estimated at $45 in quantity 1,000, according to Hitachi. This price is projected, since the SH-DSP was not shipping in volume at the time of this writing. A complete analysis of the SH-DSP, including BDTI Benchmark™ results, is included in BDTI's report, DSP on General-Purpose Processors.
|
|
|