General-Purpose Processors
|
||
General-Purpose Processors |
|
|
| HOME << |
|
|
|
||
Hitachi SH3-DSPThe Hitachi SH3-DSP is a hybrid 16-bit fixed-point DSP/32-bit RISC microcontroller architecture that targets low-cost embedded applications. Samples first became available in the first quarter of 1998, running at 133 MHz with a 1.8-volt core power supply. Volume production began in the first quarter of 1999. The SH3-DSP family consists of two family members, the SH7729 and SH7729R. The fastest members of the family run at 200 MHz. The SH3-DSP is very similar to Hitachi’s previous DSP/microcontroller hybrid, the SH-DSP. However, the SH3-DSP operates at higher clock rates, includes a memory management unit, adds several shadow registers, and has a different pipeline architecture. In the SH3-DSP, the DSP data path is primarily responsible for DSP operations and the microcontroller data path is primarily responsible for general-purpose operations. DSP data path and microcontroller operations share fifteen 32-bit general-purpose registers (R0-R14) and a hardware stack pointer (R15). The microcontroller data path has eight additional 32-bit shadow registers that shadow the first eight general-purpose registers. The DSP data path is a 16-bit fixed-point architecture that contains a 40-bit ALU, a 16 X 16 -> 32-bit multiplier, a barrel shifter, and an exponent detector. The DSP data path uses some of the shared general-purpose registers for address generation and also has exclusive access to six 32-bit operand registers (X0, X1, Y0, Y1, M0, M1). The DSP data path also contains two 40-bit accumulators (A0, A1), a status register, and various control registers. The ALU of the DSP data path can perform arithmetic operations (add, subtract, increment, decrement, negate) on 32- or 40-bit data in DSP data path registers. The ALU supports add-with-carry and subtract-with-borrow operations on 32- or 40-bit operands. The DSP data path supports logical operations (and, or, xor) on 16-bit operands in DSP data path registers. Logical operations operate on the upper 16 bits of a 32-bit register. DSP data path multiply instructions can perform a signed 16 X 16 -> 32-bit multiply operation on fractional data in a single instruction cycle. Inputs to the multiplier come from the 16 most significant bits of the DSP operand registers X0, X1, Y0, and Y1, and results are deposited into DSP registers M0, M1 (32 bits each) or A0, A1 (40 bits each, with eight guard bits). There is no multiply-accumulate instruction in the DSP data path; however, add and subtract operations can be performed in parallel with a multiply as part of a single instruction. Saturation to 32 bits is supported via a mode bit. An explicit saturation instruction is not provided. The DSP data path barrel shifter and exponent detector take operands from, and return results to, DSP operand registers. The barrel shifter can perform arithmetic shifts of up to 32 bits in either direction on 32- or 40-bit operands, and logical shifts by up to 16 bits in either direction on 16-bit operands. The exponent detector in the DSP data path can be used to compute the number of redundant sign bits in a fixed-point operand in one instruction cycle. A subsequent shift instruction can be used to normalize an operand by shifting it by the number of bits specified by the exponent detect operation. The DSP data path supports biased rounding via a special round instruction. The SH3-DSP provides a single memory space populated by several types of memory, including on-chip banks of DSP memory (X RAM, Y RAM), on-chip cache, and off-chip memory. There are four memory buses—I, L, X, and Y—and a memory management unit (MMU). The L bus is used by the cache and the MMU. Using its on-chip buses, the SH3-DSP can retrieve up to two 16-bit data words per cycle, one from X memory and one from Y memory. Thus, the 200 MHz SH3-DSP offers a peak on-chip data memory bandwidth for DSP data path operations of 400 million 16-bit words/second. The SH3-DSP contains 8 Kbytes each of X and Y RAM and a unified 16 Kbyte four-way set-associative cache. This cache uses a least-recently-used replacement policy. Instructions and data may be locked separately in the cache. The SH3-DSP external memory interface consists of a 26-bit address bus, a 32-bit data bus, and six chip-select lines. This allows the processor to access up to 384 Mbytes of off-chip memory. The external memory bus rate of the SH3-DSP is limited to half of the core clock speed, and only the I bus set can be used to access off-chip memory. Both SH3-DSP data paths support register-direct addressing, register-indirect addressing, and immediate data. In addition, the DSP data path supports modulo addressing, and the microcontroller data path supports register-indirect addressing with an immediate offset and indexed register-indirect addressing. Neither data path supports bit-reversed addressing. The SH3-DSP supports zero-overhead hardware looping. The repeat count can range from 1 to 4,095. Multiple simultaneous hardware loops are not supported, and hardware loops containing three or fewer instructions are not interruptible. All SH3-DSP family members contain the same complement of peripherals. These include serial interfaces, timers, bit I/O ports, an A/D converter, a D/A converter, and a DMA controller. The SH3-DSP operates with a typical core voltage ranging from 1.7 to 2.0 volts, depending on the family member and speed. According to Hitachi, typical operating power consumption for the core plus on-chip memory (excluding peripherals and I/O) for the SH7729R is 391 mW at 100 MHz and 1.7 volts. Power consumption for the SH7729R is 1.02 W at 200 MHz and 2.0 volts. As of October 2001, quantity 10,000 pricing for the SH7729 ranged from $10.75 to $12.90 for 100 MHz chips and from $13.40 to $15.50 for 133 MHz chips. SH7729R pricing was $10.75 for 100 MHz chips, $13.40 for 133 MHz chips, $15.75 for 167 MHz chips, and ranged from $18.40 to $20.50 for 200 MHz chips. A complete analysis of the SH3-DSP, including BDTI Benchmark™ results, is contained in BDTI's report Inside the Hitachi SH-DSP and SH3-DSP.
|
|
|