StarCore SC1200 and SC1400

The SC1200 and SC1400 are 16-bit fixed-point DSP cores announced by StarCore LLC in October 2003. (StarCore LLC is a partnership of Freescale, Agere, and Infineon.) The cores are part of StarCore’s SC1000 family of licensable, synthesizable cores. Licensees are provided with synthesizable Verilog descriptions for use in designing their own chips.

The SC1400 core architecture is based on StarCore’s earlier quad-MAC SC140 core, which was introduced in April 1999. The SC1400 and SC140 are binary compatible and offer identical performance when operating at the same clock speed and with the same memory configuration. The SC140 core, now used exclusively by Freescale and no longer offered by StarCore, is currently used in Freescale’s MSC81xx chip family. Like the SC140, the SC1400 targets a wide range of telecommunications applications, including 3G wireless and network infrastructure. The SC1400 also targets multimedia and portable applications.

The SC1200 is a scaled-down version of the SC1400, containing two MAC units instead of four. In other respects, the SC1200 and SC1400 are quite similar, and the two processors use the same instruction set. The SC1200 targets applications that demand moderate performance and require lower cost or lower power consumption, such as 2G and 2.5G cellular telephones.

According to StarCore, the SC1200 and SC1400 will achieve worst-case clock speeds of 340 MHz and 305 MHz, respectively, at 1.2 volts in a 0.13-micron process.

Architecture

The SC1000 is a VLIW architecture. The SC1400 can execute up to six instructions at a time, while the SC1200 is limited to executing a maximum of four instructions at a time because it has two fewer data paths.

Each data path on the SC1x00 (i.e., the SC1200 and SC1400) contains a combined ALU/ MAC/bit field unit (BFU). Each BFU contains a 40-bit barrel shifter. All of the data paths are identical and share a common set of sixteen 40-bit source and destination registers. Operands smaller than 40 bits are extended to 40 bits by using sign extension or zero padding. The contents of data registers can be read from or written to memory as signed or unsigned 8-bit (byte), 16-bit (word), or 32-bit (long word) operands. The SC1x00’s data paths perform single-cycle 16 × 16-bit multiplications. On the SC1400, up to four multiplications can be performed in parallel using the four data paths; the SC1200 supports up to two parallel multiplications. The multipliers support all combinations of signed and unsigned operands in both fractional and integer formats (both operands must be either fractions or integers).

Most SC1x00 instructions require a single 16-bit instruction word. However, some SC1x00 instructions and addressing modes require a second or even a third instruction word (e.g., for holding an immediate value). Instruction functionality can be extended via 16-bit prefix words. Instructions are scheduled for parallel execution at compile time by code generation tools or by the assembly language programmer. In each group of six instructions, four can specify data path operations, and the remaining two can use the address generation unit to specify program flow control instructions or perform data moves, pointer arithmetic, or bit mask operations.

The SC1x00 uses a partially interlocked five-stage pipeline. Many instructions execute with single-cycle latency; some require two cycles. The number of cycles required to execute change-of-flow instructions varies from one to six; the basic unconditional jump (JMP) requires three cycles to execute.

The SC1x00 has two 64-bit data buses and two 32-bit address buses for transferring data. Instructions are fetched via a 128-bit data bus and a 32-bit address bus. Memory is unified; any address can contain either instructions or data. Memory is byte addressable and can be accessed as either little-endian or big-endian data, controlled by a mode bit.

The 128-bit program bus allows retrieval of up to eight 16-bit instructions per cycle. (Although the architecture can only execute up to six instructions per cycle, it fetches up to eight words because some instructions require two or three words, and one or two of the 16-bit words may be used as prefixes.) The SC1x00 can perform two data reads, two data writes, or one data read and one data write per instruction cycle. Each read or write can access contiguous groups of data up to 64 bits wide. On a 305 MHz SC1x00, the maximum on-core data memory bandwidth is 2.44 billion 16-bit words/second.

The SC1x00 provides one address generation unit (AGU) containing two address arithmetic units (AAU), a bit mask unit (BMU), and a set of addressing registers. The AGU can generate two addresses per instruction cycle.

The SC1x00 supports register-direct, register-indirect, indexed, PC-relative, bit-reversed, and modulo addressing modes. Immediate data is also supported.

The SC1x00 supports up to four levels of nested hardware loops. Both single- and multi-instruction loops are supported; all loops are interruptible.

Peripherals

Power Consumption

Cost

For Additional Information

Last updated January 2005.