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Integrated Device Technology R4650

The R4650 is a general-purpose, 64-bit RISC processor family from Integrated Device Technology (IDT). The R4650 is targeted at embedded applications. The fastest versions of the family currently run at 133 MHz (133 MIPS) at 3.3 and 5.0 volts.

The R4650 is derived from IDT's R4600 processor, adding minor enhancements intended to improve performance and reduce cost in fixed-point DSP and other real-time applications. The R4650 implements the MIPS III instruction set, with additions made to accommodate the R4650's unique features. In addition, support for cache locking has been added.

The DSP-oriented enhancements found in the R4650 are useful, but quite modest in scope; the R4650 is very much a general-purpose processor.

The R4650 achieves good DSP performance with 16-bit fixed-point data. Its relatively low cost gives it cost-performance that approaches that of fixed-point DSPs.

Although the R4650 provides both integer and floating-point data paths, the integer data path provides significantly better DSP performance. The R4650 integer data path provides thirty-two 64-bit registers, all of which can be used either as operand registers or as address registers. R0 is hard-wired to a value of zero. The R4650 integer data path includes a 64x64->128-bit integer multiplier whose result is stored in or added to dedicated registers called HI and LO. HI and LO are each 64 bits in length, and are treated by the multiply instructions as a single 128-bit result register or accumulator. The lower 64 bits of the multiplier's result can also be stored in a general-purpose register directly, but this operation voids the contents of the HI and LO registers. The new integer instructions added to the R4650 to enhanced DSP performance include signed and unsigned multiply-accumulate (``MAD'') and a new multiply instruction that places its product in a general-purpose register (``MUL''). These instructions operate on 32-bit data, but automatically detect when both 32-bit multiply operands are small enough be represented using 16 bits; in such cases, instruction throughput is increased and latency is reduced. The MUL instruction stalls the pipeline for one (with 16-bit operands) or two (with 32-bit operands) instruction cycles; during this stall no other instructions can be issued. A 64-bit ALU is provided for other arithmetic and logical operations.

The HI and LO registers often become a bottleneck in DSP algorithms. This sometimes limits the utility of the MAD and MUL instructions.

The R4650 provides a single 32-bit memory space. Memory can be accessed as bytes, halfwords (16 bits), words (32 bits), or double words (64 bits). On-chip, the R4650 uses a Harvard memory architecture comprised of an on-chip instruction cache and an on-chip data cache. Each cache is eight Kbytes in size and has a dedicated bus. The R4650 supports up to one 32-bit instruction cache access and one 64-bit data cache access per instruction cycle if both the instruction and data are located in the on-chip caches. At the maximum master clock rate of 133 MHz, this equates to an on-chip data cache bandwidth of approximately 1 Gbyte/second. The R4650's external memory interface uses a single, multiplexed 64-bit bus that carries either an address or data, and has a peak bandwidth of one 64-bit read or write per bus cycle. The ratio of the external memory interface clock frequency to the instruction execution rate is between 1:2 and 1:8.

Integrated Device Technology also offers the R4640, which is identical to the R4650 but has a 32-bit external bus instead of the R4650's 64-bit external bus.

The price of a 3.3-volt, 133 MHz R4650 in a 208-pin MQUAD package, in quantity 1,000 is $63 as of October, 1996. The price of a 3.3-volt, 133 MHz R4640 in a 128-pin PQFP package, in quantity 1,000 is $34 as of October, 1996.

A complete analysis of the R4650, including estimated BDTI Benchmark™ results, is contained in BDTI's report, DSP on General-Purpose Processors.

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