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DSP Group PineDSPCore
The DSP Group PineDSPCore is a 16-bit fixed-point licensable DSP core
that is aimed at low-cost, low-power applications such as cellular
telephones and pagers. Introduced in 1992, the PineDSPCore is the
first DSP core from DSP Group. DSP Group rates it at 40 MIPS at 3.3 or
5.0 volts, but licensees have achieved up to 80 MIPS.
The core is intended to be used in application-specific integrated
circuits (ASICs); ASIC designers customize the amount of memory and
selection of surrounding peripherals. The PineDSPCore itself can
include up to two Kwords of on-core memory, but includes no
peripherals. DSP Group provides a number of peripheral macrocells,
including 8- and 16-bit host interfaces, SRAM/EPROM/DRAM interfaces, a
timer, and a serial port.
Assembly code written for the PineDSPCore can be reassembled and used
on its successor, the OakDSPCore, without
modification.
DSP Group concentrates on licensing the PineDSPCore to high-
volume end users and to semiconductor vendors who will use it in
their application-specific products.
The PineDSPCore is suitable for moderate-performance applications.
Its main shortcomings are that one bank of memory is not expandable
off-core and that it only provides two off-core interrupt lines.
The data path of the PineDSPCore supports fractional and integer
arithmetic and includes a 16x16->32-bit signed/signed multiplier, a
36-bit ALU, and a shifter capable of single- and four-bit left and
right shifting. The PineDSPCore provides two 36-bit accumulators, six
16-bit address/general-purpose registers, and two address modifier
registers. Multiplication operands come from two 16-bit multiplier
input registers and the product is stored in the 32-bit product
register.
The PineDSPCore provides two memory spaces: one for program memory and
one for data. The program memory space uses a set of two 16-bit buses
to access up to 64 Kwords of off-core program memory. The data memory
space has two individual bus sets that are each connected to up to one
Kword of on-core memory. One of the data bus sets is read-only and
supplies operands for the multiplier; the other data bus set can be
extended off-core to address up to 62 Kwords of off-core memory. Each
on-chip bus set allows one access per instruction cycle.
For detailed information about the PineDSPCore including benchmark
results and analysis, contact BDTI.
See also: OakDSPCore.
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