The Pentium is fully binary-compatible with its predecessors, i.e., programs written and compiled for any earlier 80x86 family member produce identical results when executed on the Pentium. The Pentium contains no DSP-oriented features. However, due to its high instruction execution rate it achieves good performance on floating-point DSP applications. Optimizing DSP code for the Pentium is very challenging, even by DSP processor standards. In addition, the processor's many dynamic features make it very difficult to guarantee the execution time of DSP software, complicating real-time development. The Pentium offers a widely known instruction set, a large number of software and hardware development tools, and wide availability and diversity of hardware support (chips, boards, test equipment, and documentation).
The Pentium is a superscalar (two-issue) 32-bit processor with 16 Kbytes of on-chip cache (8 Kbytes instruction, 8 Kbytes data). There are two integer units named U and V. There is a single floating-point unit which shares some resources with the U unit. Although the integer and floating-point units are capable of independent operation, a maximum of two integer instructions or a single floating-point operation may be issued during a single instruction cycle. The integer data path of the Pentium consists of eight 32-bit general-purpose integer registers (including the stack pointer, ESP) and two ALUs (one for each integer unit). The ALUs support signed or unsigned (but not mixed signed/unsigned) integer operations on 8-, 16-, and 32-bit operands, including multiplication and division. The Pentium floating-point unit (FPU) performs operations on 32-, 64-, and 80-bit operands. Pentium floating-point operations conform to IEEE standards 754 and 854. When a floating-point operand is loaded into the FPU, it is converted to 80 bits and all operations inside the FPU are carried out using an 80-bit data width. There are eight 80-bit FPU registers arranged as a LIFO stack. FPU operations specify only a single memory or stack operand; the second operand is always fetched from the top of the stack. The floating-point register exchange (FXCH) instruction is used to swap the top of the stack with another floating-point register. The Pentium uses a single 32-bit, byte-addressable address space with two 8-Kbyte on-chip level-one (L1) caches. Both caches are two-way set associative with 32-byte line sizes. The data cache can be configured as write-through or write-back on a line-by-line basis. The on-chip data cache allows loading or storing two 32-bit integer operands, or loading one 32- or 64-bit floating-point operand in one instruction cycle. The Pentium's external memory interface provides a 64-bit-wide path from the on-chip L1 caches to main memory or to an off-chip level-two (L2) cache. A separate 29-bit address bus is provided. The three least-significant bits of the 32-bit address are omitted from the external interface since all external memory accesses are eight-byte aligned. This interface is pipelined to allow two simultaneous bus requests. Currently, the maximum memory bus speed is 66 MHz. The external memory interface has a peak bandwidth of one 64-bit read or write per bus cycle, assuming pipelined burst reads or writes are used. The Pentium contains two address generation units, one each for the U and V units. Addresses are comprised of two main components: a segment and an offset. The segment portion provides the starting address of a segment (partition) of memory. There are two main modes for determining the starting address of a segment: real mode and protected mode. In real mode the maximum addressable memory is based on 20-bit addresses, or 1 Mbyte; in protected mode, 32-bit addresses, or 4 Gbytes. As of December, 1997, quantity 1,000 prices for Pentium processors range from $106 to $509, depending on the speed grade. For example, the 200 MHz Pentium with a plastic PGA package is priced at $509. A complete analysis of the Pentium (and also the MMX Pentium), including the BDTI Benchmark™ results, is contained in BDTI's report, DSP on General-Purpose Processors.
Berkeley Design Technology, Inc. (BDTI) 2101 Webster Street, Suite 1450 Oakland, CA 94612 U.S.A. Tel: +1 (510) 451-1800 Fax: +1 (510) 451-1885 info@BDTI.com Address comments and suggestions about this site to webmaster@BDTI.com Copyright © 1999-2008 Berkeley Design Technology, Inc.
