DSP Cores
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DSP Group OakDSPCoreThe DSP Group OakDSPCore is a 16-bit fixed-point licensable DSP core aimed at low-cost, low-power applications such as cellular telephones and pagers. The OakDSPCore was introduced in 1994 as a successor to the PineDSPCore. DSP Group rates it at 40 MIPS at 3.3 or 5.0 volts, but licensees have achieved up to 80 MIPS. The core is intended to be used in application-specific integrated circuits (ASICs); ASIC designers customize the amount of memory and selection of surrounding peripherals. The OakDSPCore itself can include up to four Kwords of on-core memory, but includes no peripherals. DSP Group provides a number of peripheral macrocells, including 8- and 16-bit host interfaces, SRAM/EPROM/DRAM interfaces, a timer, and a serial port. The architecture of the OakDSPCore is quite similar to that of its predecessor, the PineDSPCore. Assembly-language code written for the PineDSPCore can be reassembled for the OakDSPCore without modification. DSP Group concentrates on licensing the OakDSPCore to high- volume end users and to semiconductor vendors who will use it in their application-specific products. The OakDSPCore is suitable for moderate-performance applications. Its main shortcoming is that one bank of memory is not expandable off-core. Note, however, that several OakDSPCore licensees have removed this limitation. See below for further details. The data path of the OakDSPCore supports fractional and integer arithmetic and includes a 16x16->32-bit signed/signed, signed/unsigned, and unsigned/unsigned multiplier; a 36-bit ALU, a 36-bit barrel shifter, and a bit-manipulation unit. The OakDSPCore provides four 36-bit accumulators (of which two are used only by the bit-manipulation unit), six 16-bit address/general-purpose registers, and two address modifier registers. Multiplication operands come from two 16-bit multiplier input registers and the product is stored in the 32-bit product register. The OakDSPCore provides two memory spaces: one for program memory and one for data. The program memory space uses a set of two 16-bit buses to access up to 64 Kwords of off-core program memory. Writes to program memory are supported. The data memory space has two individual bus sets that are each connected to up to 2 Kwords of on-core memory. One of the data bus sets (Y) is read-only and supplies operands for the multiplier, and cannot be extended off-core*. The other data bus set (X) can be extended off-core to address up to 62 Kwords of off-core memory. Each on-chip bus set allows one access per instruction cycle.
* In our original write-up on the OakDSPCore, the Y data bus set
could not be extended off-core. However, several OakDSPCore licensees
have recently fabricated OakDSPCore-based devices that remove this
limitation, and allow the Y bus set to be extended off-core to address
a maximum of 32 Kwords. The total amount of addressable off-core
memory has not increased; any increase in addressable Y memory must be
compensated by a decrease in addressable X memory so that the total is
not greater than 64 Kwords. For detailed information about the OakDSPCore including benchmark results and analysis, contact BDTI. See also: PineDSPCore. |
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