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NEC Electronics μPD77050 (SPXK5)

The μPD77050 is a 16-bit fixed-point VLIW DSP processor chip based on the NEC Electronics SPXK5 core, introduced in 2001. The μPD77050 supports speed/voltage scaling. The μPD77050 is currently in full production and can operate at speeds/voltages ranging from 180 MHz at 0.9 volts through 250 MHz at 1.5 volts. The μPD77050 targets low-power mobile applications such as cellular phones, PDAs, and digital video cameras.

The μPD77050 is the successor to NEC’s μPD77016 and μPD77116 processors, which are based on the single-issue SPXK3 and SPXK4 cores, respectively. The SPXK5 is partly assembly-compatible with these earlier families.

Architecture

The SPXK5 core is based on three main components: an “execution block,” a “data address block,” and a “system control block.” The execution block contains two 16-bit MAC units, two 40-bit ALUs, and eight 40-bit general-purpose registers. Each of the general-purpose registers can be accessed as two 16-bit registers and an 8-bit register by appending “H” (high 16 bits), “L” (low 16 bits), or “E” (upper 8 bits) to the register name. The data address block contains two load/store units and a variety of addressing registers. The system control block controls program sequencing; it is responsible for fetching and dispatching instructions and for looping, branching, and interrupts.

The SPXK5 can issue and execute up to four 16-bit instructions in parallel. These instructions can use any of the four execution units (two ALUs and two MAC units), the two load/store units, and the system control block.

The 16-bit multiply-accumulate units support signed or unsigned 16-bit multiply, multiply-accumulate, and multiply-subtract. In addition, there is a specialized multiply-accumulate instruction that performs a 16-bit arithmetic right-shift of the accumulator (i.e., a 40-bit general-purpose register) prior to accumulation, which facilitates double-precision arithmetic. There are also variants of the multiply-accumulate and multiply-subtract instructions that specify rounding. Saturation is available for most multiply-accumulate instructions via a mode bit.

In general, any of the general-purpose registers can be used as sources or destinations. There are a few exceptions; e.g., if saturation is used in combination with a rounding multiply-accumulate instruction, only the first four registers can be used as sources or destinations.

The 40-bit ALUs support a range of operations including addition and subtraction, absolute value, and, not, or, xor, negate, compare, exponent detection, and iterative divide. They also support register-to-register moves of 40-bit values. The ALUs perform shifting operations, including logical left or right shifts and arithmetic right shifts of up to 39 bits. The SPXK5 ALUs support several dual 16-bit SIMD operations, including addition, subtraction, maximum, minimum, and one- or two-bit arithmetic right shift. The SIMD maximum and minimum instructions update “Viterbi history registers” and “Viterbi history pointer registers,” and are useful for accelerating Viterbi decoding.

The ALUs also provide several instructions intended to support video applications, including instructions that pack and unpack 8-bit quantities and a “clip” instruction.

The SPXK5 uses a Harvard memory architecture with one 64-bit instruction bus, three 32-bit address buses, and two 32-bit data buses. The SPXK5 also includes a 32-bit “main bus” used for register-to-register transfers and for providing a path from the execution and data address blocks to the system control block. The μPD77050 chip contains a 16 Kbyte instruction cache in addition to 64 Kbytes of instruction memory and 64 Kbytes of data memory. The processor can transfer up to two 16- or 32-bit data words between memory and registers per cycle. Thus, the maximum data bandwidth at 250 MHz is 1 billion 16-bit words per second for reads or writes, assuming 16-bit data words are arranged as pairs in memory.

The data address unit (DAU) contains two ALUs that can generate two independent addresses per cycle. It also includes eight 32-bit data pointer registers, eight 16-bit index registers, and two 16-bit registers used for modulo addressing. The DAU can transfer up to two 16- or 32-bit words between memory and general-purpose registers per cycle. Loading 32-bit words requires data to be aligned on 32-bit boundaries.

Addressing modes include register direct, register-indirect with pre- or post-modification, modulo addressing, and bit-reversed addressing. The SPXK5 also supports data pointer arithmetic instructions, such as pointer addition and subtraction. The processor also supports immediate data.

The SPXK5 supports up to four levels of hardware looping. Hardware loops must contain at least two execution packets (that is, two very long instruction words) and are interruptible.

Peripherals

The μPD77050 peripherals include an eight-channel DMA controller, an AHB interface, an SDRAM interface, a TSA (time slot assigner) serial interface, an audio serial interface, a host interface, a timer, and 16 general-purpose I/O pins.

Power Consumption

According to NEC, the μPD77050 consumes 98 mW at 150 MHz and 0.9 volts. These power measurements are based on a DSP workload and include the processor core and on-chip memory but no peripherals.

Cost

As of the last quarter of 2004, pricing for the μPD77050 is $15.00 in 10,000-unit quantities.

For Additional Information

The μPD77050 achieves a BDTIsimMark2000™ score of 1770 at 250 MHz. For more information and scores, click here. Additional analysis of this processor, including BDTI Benchmark™ results, is contained in BDTI’s report, Inside the Intel PXA27x.

Last updated January 2005.

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