NEC uPD7701x

NEC's uPD7701x DSP processor family is based on a 16-bit fixed-point architecture with a 32-bit instruction word. The first member of the family, the RAM-based uPD77016, was announced in 1991. According to NEC, this part is intended only for code development and debugging purposes for the ROM-based family members and thus, some design considerations (such as power consumption) were given less weight. This part uses a 5.0-volt nominal supply and operates at up to 33 MIPS. The ROM-based uPD7701x family members include the uPD77015, uPD77017, and uPD77018. These processors use 3.0-volt nominal supplies and operate at up to 33 MIPS, as of March 1997. The uPD7701x family is targeted at high-performance wireless and telecommunications applications such as digital cellular telephony and modems. According to NEC, new uPD7701x family members are currently under development that will execute at up to 52 MIPS.

The uPD7701x data path is made up of three main execution units: a 40-bit multiply-accumulate unit, a 40-bit ALU, and a 40-bit barrel shifter. Each unit is capable of single-cycle execution, but only one unit can be active at a time. The multiply-accumulate unit incorporates a 16x16->32 multiplier integrated with a 40-bit accumulator providing eight guard bits. Additionally, the data path of the uPD7701x has eight 40-bit general-purpose registers, which are used for source and destination operands for all arithmetic operations. This corresponds to having eight accumulators that each provide eight guard bits. The uPD7701x implements a load-store architecture; operands must be loaded to registers before use. Similarly, the results of arithmetic operations must be stored to a register. However, the uPD7701x allows the use of 16-bit immediate data operands with some instructions. The multiplier supports fractional multiplication for signed/signed, signed/unsigned, and unsigned/unsigned operands by left-shifting the data before accumulation. The barrel shifter is capable of performing a 0-40 bit arithmetic or logical left or right shift in a single instruction cycle. The uPD7701x data path also supports normalization via exponent detect and barrel shift operations.

The uPD7701x features an enhanced Harvard architecture with three separate memory spaces: a program memory space and two data memory spaces (X and Y). The program memory space uses a 32-bit program data bus and a 16-bit program address bus, while each data memory space has its own 16-bit data and 16-bit address bus on-chip. On-chip memory configurations vary from processor to processor.

In general, NEC uPD7701x processors support three on-chip memory accesses per instruction cycle: one for instructions and two for data. Thus, the maximum sustainable on-chip data memory bandwidth for a 33 MIPS uPD77015 is 66 Mwords/second. However, the processor places limitations on the circumstances under which two data memory accesses are possible. In particular, attempts to simultaneously access two values in external memory, or (on processors that have internal ROM) attempts to simultaneously access two values in internal ROM or one value in internal ROM and one value in external memory will fail.

The uPD77016 provides two external memory interfaces: one for program and one for data. The uPD77015, uPD77017, and uPD77018 provide a single external memory interface, which is used only for data. Bus widths vary based on the family member. All members of the uPD7701x family are capable of accessing one off-chip data memory operand in a single instruction cycle. This results in an external data memory bandwidth of 33 Mwords/second on a uPD7701x running at 33 MIPS.

The processor provides separate address generation units for X and Y memory. Each unit consists of a 16-bit ALU for address calculations, four 16-bit address registers, and four 16-bit modifier registers. In addition, one modulo register is provided by each unit to support circular addressing. Other addressing modes available on the uPD7701x include memory-direct, register-direct, and register-indirect. Immediate data is also supported.

The uPD7701x provides both single- and multi-instruction hardware loops through the REP and LOOP instructions.

Peripherals include two synchronous serial ports, an eight-bit host port, and a four-bit bit I/O port. Unlike most DSPs, the uPD7701x does not provide a timer.

As of March 1997, quantity 1,000 pricing for the 33 MIPS, 3.0-volt uPD77018 is $25.00 in a 100-pin TQFP. For a complete evaluation of this processor, including BDTI Benchmark™ results, contact BDTI.