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Motorola DSP96002

The Motorola DSP96002 is a 32-bit IEEE standard 754 floating-point processor with 32-bit integer support. Introduced in 1988, the DSP96002 is Motorola's only floating-point DSP processor. It has an overall architecture similar to that of the Motorola DSP560xx family.

The fastest versions of the processor execute at 20 MIPS. In 1993, Motorola introduced a new version of the processor that allows its 1Kx32 on-chip program RAM to be reconfigured as an instruction cache.

The DSP96002 has achieved popularity in some scientific and military applications (especially those involving the fast Fourier transform), but has not found widespread use elsewhere.

The DSP96002 is notable for its full hardware support of IEEE-754 single-precision and single-extended-precision floating-point arithmetic, its two complete sets of external 32-bit address and 32-bit data buses, and its lack of common on-chip peripherals.

The execution units in the DSP96002's data path are a multiplier, an adder/subtracter unit, a logic unit, and a barrel shifter. The same data path is used to support both integer and floating-point arithmetic. The multiplier accepts 44-bit floating-point values as input and produces a 44-bit floating-point value as output, while for integer arithmetic it takes in 32-bit values and produces a 64-bit result. The adder/subtracter units operate on 32-bit data and produce 32-bit results. The barrel shifter can shift 32-bit data left or right by up to 32 bits. The logic unit handles logic operations (and, or, etc.) on 32-bit data.

Ten 96-bit registers (each broken up into three 32-bit portions) serve as the sources and destinations of data path operations. The last two of these are never used as sources for data path operations; they instead serve as destination registers for simultaneous add/subtract operations, useful in FFTs.

The DSP96002 features the most complete IEEE floating-point implementation of all DSP processors.

The DSP96002 provides three memory spaces: program memory, X data memory, and Y data memory. Each memory space has its own set of on-chip 32-bit address and data buses. The processor also has two other on-chip data buses: the global data bus and the DMA data bus.

On-chip memories include a 1Kx32 program RAM, a 512x32 X data RAM, a 512x32 Y data RAM, a 512x32 X data ROM, and a 512x32 Y data ROM. All of the on-chip memories and all three on-chip address buses permit two accesses per instruction cycle. This allows the DSP96002 to perform three processor data accesses (one instruction fetch and two data accesses) in addition to a DMA access to or from any memory space per instruction cycle.

The DSP96002 features two identical, independent sets of external buses called expansion ports. Each expansion port has a 32-bit address bus, a 32-bit data bus, and control lines. Each memory space (X, Y, and P) is divided into eight equal-sized regions, and each region can be assigned to one of the expansion ports for external memory access. The processor supports two external memory accesses per instruction cycle. Bus strobes are provided that indicate whether the processor is making a program, X data, or Y data access.

The DSP96002's two identical 32-bit external memory ports are an unusual feature that benefits large multiprocessor applications.

According to Motorola, May 1997 prices for the DSP96002 range from $52.50 to $56.00 in quantity 1,000.

For detailed information on the Motorola DSP96002 including benchmark results and analysis, contact BDTI.

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