Fixed-Point DSP Processors
|
||
Fixed-Point DSP Processors |
|
|
| HOME << |
|
|
|
||
Motorola DSP566xxThe DSP566xx family is a 16-bit version of Motorola's 24-bit fixed-point DSP563xx family. The DSP566xx retains a 24-bit instruction set that is almost identical to that of the DSP563xx, but Motorola has reduced the width of the processor's address buses, data buses, and data path from 24 bits to 16 bits. In 1998, Motorola announced two new family members, the DSP56651 and DSP56652, which integrate a DSP56600 DSP core with a 32-bit RISC MCORE microcontroller to provide for single-chip cellular baseband applications. As of October 1998, DSP566xx family members operate at a maximum speed of 70 MIPS at 2.5 volts. Motorola introduced the DSP566xx in 1995 for mobile wireless communications applications that use software based on the DSP563xx 24-bit instruction set but need only 16 bits of precision. Narrowing the data width to 16 bits allowed Motorola to reduce the silicon area and power consumption of the DSP566xx in comparison to the DSP563xx, both important concerns for mobile wireless applications. With the exception of a few substitutions in the instruction set and changes in instruction execution order restrictions, the DSP566xx is object-code compatible with the DSP563xx operating on 16-bit data values (i.e., when the DSP563xx is in 16-bit compatibility mode). Because the two processors are so similar, this analysis highlights only the differences between the DSP563xx and the DSP566xx. Readers should refer to the DSP563xx analysis for a discussion of its architecture. The DSP566xx data path only supports 16-bit data operations. The results of DSP566xx data path operations are identical to DSP563xx operations when the DSP563xx is in 16-bit arithmetic mode (with the exception of small differences in the instruction set and restrictions on instruction execution order). The DSP566xx memory system differs from that of the DSP563xx in the width of data and address buses and sizes of on-chip memory banks. With the exception of the program data bus, Motorola reduced the width of all internal data and address buses from 24 bits to 16 bits. Occasionally, programmers may wish to read or write data to 24-bit program memory. When moving 16-bit data to a 24-bit memory location, the DSP566xx extends the 16-bit data with the lower 8 bits of a special bus switch register. Thus, programmers wishing to write 24 bits of data to program memory should first write the 8 MSBs to the lower half of the bus switch register and then initiate the data move. Likewise, when copying data from a 24-bit program memory to a 16-bit register, the DSP566xx copies only the lower 16 bits to the destination register. The 8 MSBs are copied to the bus switch register. An unusual feature of the Motorola DSP566xx is that it allows up to four ROM code patches. ROM patching allows incorrect sections of program ROM to be replaced with program RAM loaded by a bootstrap procedure. If the execution order of the incorrect instructions in ROM is known, more than four code patches may be enabled by using the patch code to reprogram the ROM patch instruction registers. The DSP566xx external memory interface, called an expansion port, differs from that of the DSP563xx in several ways, including the following: First, Motorola replaced the 24-bit external address bus on the DSP563xx with a 16-bit external address bus. Second, the DSP566xx external memory interface supports only static RAM (SRAM). In contrast, the DSP563xx external memory interface also supports synchronous static RAM (SSRAM) and dynamic RAM (DRAM). The lack of support for SSRAM is especially significant because SSRAM is the only memory fast enough to support zero-wait-state access on the DSP563xx and DSP566xx. Thus, although the DSP563xx can read or write external data with a throughput of one word per instruction cycle, external data memory accesses require at least one wait state on the DSP566xx. Therefore, the maximum external memory data bandwidth on the DSP566xx is one word per two instruction cycles, or 30 Mwords/second on a DSP5660x running at 60 MIPS and 35 Mwords/second on a DSP5665x running at 70 MIPS. In contrast, a DSP563xx running at 60 MIPS has a maximum external memory data bandwidth of 60 Mwords/second when using SSRAM. External instruction fetches also require at least one wait state. The DSP566xx does not include an instruction cache or DMA, both found on the DSP563xx. The DSP566xx supports the same addressing modes as the DSP563xx. None of the current DSP566xx family members include the PCI bus interface found on the DSP56301. Rather, the DSP56602 and DSP56603 both include the 8-bit host interface found on the DSP56302 and DSP56303. The DSP56602 and the DSP56603 also include a synchronous serial port (SSI), three timers and three dedicated bidirectional bit input/output pins. As of October 1998, quantity 10,000 prices for DSP566xx family members range from $15.00 to $60.00. A complete analysis of the DSP566xx, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition.
|
|
|