Freescale DSP563xx

The DSP563xx family, introduced in 1995, is Freescale’s second generation of 24-bit fixed-point DSP processors. The DSP563xx architecture is similar to (and object-code upward compatible with) its predecessor, the DSP560xx family, but includes significant modifications designed to increase performance. The fastest DSP563xx family member runs at 275 MHz at 1.6 volts. The DSP563xx targets a variety of applications including high-fidelity audio applications, which benefit from its wider data word width compared to 16-bit DSPs.

Architecture

The DSP563xx data path features an integrated MAC/ALU with a 24 × 24 → 48-bit multiplier, a 56-bit ALU, and two 56-bit accumulators with eight guard bits. All arithmetic and multiplication instructions execute with single-cycle throughput and two-cycle latency. The DSP563xx data path uses fractional arithmetic in all multiplication operations. To perform integer multiplication, programmers must convert the result of a fractional multiply to integer format by shifting a sign bit into the accumulator’s most significant bit.

The DSP563xx provides a barrel shifter and bit-field manipulation unit to allow multi-bit shifting and bit-field insert and extract operations.

The DSP563xx architecture divides memory into three spaces: program space, X data space, and Y data space. Each memory space has a separate 24-bit on-chip address bus and 24-bit on-chip data bus. Additionally, each memory space is associated with one or more dedicated banks of on-chip ROM or RAM.

The three memory spaces with their dedicated data and address buses allow DSP563xx processors to make three memory accesses per instruction cycle without the use of a cache. The on-chip program memory permits one instruction fetch per instruction cycle, while the on-chip data memories permit two reads, two writes, or one write and one read per instruction cycle. Thus, when the processor is executing at 275 MHz, the maximum sustainable on-chip data memory bandwidth is 550 million 24-bit words/second.

The DSP563xx supports immediate data and register-direct, memory-direct, and register-indirect addressing modes. The processor also supports short-address versions of these modes for certain instructions.

The DSP563xx provides two instructions for hardware loops: REP and DO. The former repeats a single one-word instruction, while the latter repeats a block of instructions. In both cases, instructions can be repeated from 0 to 65,535 times. Additionally, the DO FOREVER instruction repeats code fragments indefinitely. The DO loop can repeat a code fragment as large as program memory.

Peripherals

Power Consumption

Cost

For Additional Information

Last updated January 2005.