
Fixed-Point DSP Processors
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Motorola DSP560xx

The Motorola DSP560xx family consists of several 24-bit fixed-point DSPs based on a common core architecture. The family is popular in digital audio applications, where its 24-bit word width improves dynamic range and reduces quantization noise compared to 16-bit fixed-point DSPs. As of October 1998, the fastest processor in the family executes at 47.5 MIPS at 5.0 volts.

The DSP56000 and DSP56001 were the first members of the DSO560xx family, and were introduced in 1987. In 1992, Motorola introduced the DSP56002. In late 1994, Motorola phased out the DSP56000 and DSP56001, replacing them with the DSP56001A. Motorola is no longer recommending that new designs be based on the DSP56001A, however, and this processor is not included in our analysis. Similarly, Motorola is no longer recommending the DSP56005 for new applications, so we have also removed this processor from our analysis. In 1996, Motorola introduced the DSP56011, targeted specifically at audio decoding for DVD (Digital Versatile Disc) players.

The DSP560xx has a 24-bit, fixed-point data path that features an integrated MAC/ALU with a 24x24->48-bit multiplier, a 56-bit ALU, and two 56-bit accumulators that each provide eight guard bits. The DSP560xx data path uses fractional arithmetic in all operations. Because the DSP560xx does not have an integer multiply instruction, performing an integer multiply requires programmers to convert the result of a fractional multiply to integer format by shifting a sign bit into the accumulator MSB.

The data path can shift values one bit left or right. No barrel shifter is available, but the DSP560xx does support signed multiplies by a specified immediate fractional power of 2, resulting in the equivalent of an arithmetic right shift. The DSP560xx provides a carry bit which is updated by shifting and ALU operations.

The data path provides support for 48-bit double-precision arithmetic. The processor supports convergent rounding, which can be optionally applied to output values of the MAC/ALU unit before they are stored in an accumulator. This reduces bias caused by conventional rounding techniques.

The DSP560xx architecture divides memory into three spaces: program (P) space, X data space, and Y data space. Each memory space has a separate 16-bit address bus and 24-bit data bus on-chip. Additionally, each memory space is associated with one or more dedicated banks of on-chip ROM or RAM. Memory is word-addressable. The three on-chip memories with their dedicated data and address buses allow DSP560xx processors to make three memory accesses (one instruction fetch and two data accesses) per instruction cycle without the use of a cache. This memory bandwidth, coupled with the processor's instruction set, also allows single-cycle double-precision (i.e., 48-bit) transfers between memory and accumulators, facilitating extended-precision arithmetic.

The on-chip program memory permits one instruction fetch per instruction cycle, while the on-chip data memories permit two reads, two writes, or one write and one read per instruction cycle. Thus, when the processor is executing at 47.5 MIPS, the maximum sustainable on-chip data memory bandwidth is 95 Mwords/second.

Externally, the DSP56002 provides one 24-bit data bus and one 16-bit address bus. The three sets of internal buses are multiplexed onto the external buses. Separate read, write, program, and X/Y data memory selects are provided. Assuming zero wait-state external memory, the processor can execute one external memory access per instruction cycle. The external access can be for either data or program memory. Thus, at a speed of 47.5 MIPS, the DSP560xx has an external memory bandwidth of 47.5 Mwords/second. Programmed and externally requested wait states are supported.

The DSP560xx supports register-direct, memory-direct, and register-indirect addressing modes, and also supports short address versions of these modes for certain instructions. Immediate data is supported.

The DSP560xx provides two instructions for hardware loops: REP and DO. The former repeats a single one-word instruction, while the latter repeats a block of instructions.

All DSP560xx processors except the DSP56004 and DSP56007 provide one synchronous and one asynchronous serial port, a timer, and an 8-bit host interface port for communication with a general-purpose processor or similar device. The 24 pins used for these serial ports, timer, and host interface can also be used as general-purpose bit I/O pins if the peripheral to which they are assigned is not in use or doesn't require all of the pins assigned to it.

As of October 1998, quantity 10,000 prices for DSP560xx family members range from $8.00 to $21.00. A complete analysis of the DSP560xx, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 1999 Edition.

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