General-Purpose Processors
|
||
General-Purpose Processors |
|
|
| HOME << |
|
|
|
||
Intel MMX PentiumThe Intel MMX Pentium (designated the ``Pentium with MMX Technology'' by Intel), formally introduced in 1997, is a 32-bit, two-issue superscalar CISC general-purpose processor with support for fixed-point and floating-point arithmetic. The architecture of the MMX Pentium is the same as that of the original Pentium except for number of improvements, the most visible of which are deeper pipelines, larger caches, improved branch prediction, and 57 new instructions intended for DSP, image, and video processing—the MMX instructions. Like the original Pentium, the MMX Pentium is targeted at desktop and mobile personal computers. The MMX Pentium is expected to replace the original Pentium during the course of 1997. As of May 1997, the fastest versions of the MMX Pentium run at 200 MHz using a dual 2.8- and 3.3-volt supply. The MMX Pentium is object-code compatible with its predecessors in the Intel 80x86 family, and object code written for the MMX Pentium can be executed on the Pentium II. The MMX instruction set extensions enable the MMX Pentium to achieve better execution time performance than most high-end DSP processors. As in the original Pentium, the MMX Pentium provides both a fixed-point integer data path that allows up to two operations to be executed simultaneously, and a floating-point data path that allows one operation to be performed at a time. In addition, the MMX Pentium provides a new MMX data path that allows up to two MMX operations to execute simultaneously, or up to one MMX operation and one integer operation (in the integer data path) to execute simultaneously. The integer data path includes two ALUs and supports operations on 8-, 16-, and 32-bit integers. The integer data path uses eight registers for operands and results, but imposes several restrictions on which registers can be used by the various operations. The floating-point data path supports 32-, 64-, and 80-bit operands and is fully IEEE 754 and 854 compliant. The floating-point data path uses eight dedicated floating-point registers that are organized as a stack. In general, using the floating-point data path for DSP operations yields faster implementations than using the integer data path. The MMX data path includes two 64-bit ALUs, one barrel shifter, one integer memory/register access unit, and one multiplier capable of performing four 16x16->32-bit multiplications in a single instruction cycle. MMX instructions operate on eight MMX registers. Each MMX register can be treated as either one 64-bit word, two 32-bit words, four 16-bit words, or eight 8-bit bytes. MMX instructions are ``single instruction multiple data'' instructions that operate on the 64-bit-wide MMX registers or on memory in one of the above configurations. The MMX Pentium provides a 32-bit address space and uses instruction widths varying between 1 and 15 bytes. The processor provides two 16-Kbyte on-chip caches for instructions and data. Assuming no bank conflicts, the data cache allows loading or storing two 32-bit integer operands or loading one floating-point operand per instruction cycle. Storing a floating-point operand takes two instruction cycles. The processor provides a 64-bit-wide path from the on-chip caches to external memory. A 29-bit external address bus is also provided. The maximum external bus speed is 66 MHz. Memory addresses are comprised of a segment and an offset, specified in separate address registers. Two main modes of operation, real mode and protected mode, determine how the starting address of a segment is calculated. The MMX Pentium provides flexible addressing modes compared to those found on many general-purpose processors. The 200-MHz MMX Pentium was introduced in January, 1997 at a price of $550.00 in quantity 1,000, using a 296-pin ceramic or plastic PGA package. A complete analysis of the MMX Pentium, including estimated BDTI Benchmark™ results, is contained in BDTI's report, DSP on General-Purpose Processors.
|
|
|