
Fixed-Point DSP Processors
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Motorola DSP568xx

The Motorola DSP568xx family is based on Motorola's DSP56800 16-bit fixed-point DSP core. The members of the DSP568xx family operate at a maximum of 35 MIPS using a supply voltage of 3.0-3.3 volts (+/- 10%). Motorola DSP568xx processors are targeted at low-cost, low-power applications in mobile, wireless, and wireline communications where both signal processing and control features are necessary. Examples of these applications include digital messaging systems, RF modems, and digital answering machines.

The DSP568xx family's data path is based on a single-cycle 16x16->32-bit multiplier integrated with a 36-bit ALU. Two 36-bit accumulators are provided by the DSP568xx, each with four guard bits for overflow protection. ALU operations execute in a single cycle, assuming all operands are registers. The MAC/ALU unit together with a logic unit performs all multiplication, addition, subtraction, logical, and other arithmetic operations except shifting. Besides integer multiplication, the multiply-accumulate unit supports signed and signed/unsigned fractional multiplication; unsigned/unsigned multiplication is not supported. The MAC/ALU unit features a carry bit supporting extended-precision arithmetic and rotate-through-carry operations. Also included are an accumulator shifter and a 16-bit barrel shifter. Bit manipulations on data memory words, peripheral registers, and all registers within the core are performed by a dedicated bit-manipulation unit that is capable of testing, setting, clearing, or inverting any bits specified in a 16-bit mask.

The data path supports both convergent and round-to-nearest rounding via dedicated rounding instructions.

The DSP568xx features saturation circuitry that is used to detect 36-bit accumulator values whose magnitude will not fit in a 16-bit destination. In this case, the processor saturates the higher 16-bit portion of the accumulator to a 2's complement representation of +/- 1.0 when the value is transferred out of the accumulator.

The DSP568xx family uses separate 16-bit program (P) and data (X) address spaces and separate on-chip program and data memories. Internally, data memory can be accessed using two separate buses: the Core Global Data Bus (CGDB) and the Data (X) Data Bus 2. Only the Core Global Data Bus can be used to access external data memory. The data memory address buses are all 16 bits wide. The width of the internal program memory address bus is 19 bits, which supports expansion of the external program memory by up to 512 Kwords. Although this memory expansion capability is not available with current family members, the 16-bit program counter of the core can be extended to 19 bits using 3 bits stored in a status register, thus supporting larger program space in future family members.

The on-chip program memory permits one instruction fetch per instruction cycle, while the on-chip data memory permits two reads or one write per instruction cycle. Thus, when the processor is executing at 35 MIPS, the maximum sustainable on-chip data memory bandwidth is 70 Mwords/second for reads and 35 Mwords/second for writes.

The external memory interface of the DSP568xx is made up of a 16-bit address bus and a 16-bit data bus. These buses are multiplexed between program and data memory accesses. Program/data and read/write strobes indicate the type of bus cycle. One off-chip access can be made without penalty in a single instruction cycle, assuming zero wait states. Because only one of the two data (X) address buses is connected to the external memory interface, only one data memory access to the external memory can be made by a single instruction. Thus, the second read in a dual parallel read must be made from on-chip memory. Assuming zero wait states, the maximum peak and sustainable external memory bandwidth of the DSP568xx is 35 Mwords/second when the processor is executing at 35 MIPS.

The DSP568xx family supports immediate data, and memory-direct, register-direct, and register-indirect addressing modes. The processor also supports six-bit short immediate data and short memory-direct addresses for some instructions. Circular addressing is supported, and two circular buffers can simultaneously be active. The address generation unit is not capable of bit-reversed addressing.

Hardware looping is supported in DSP568xx family processors via the REP and DO instructions.

The DSP568xx peripherals include two general-purpose bit I/O ports, one synchronous serial interface, two "peripheral serial interfaces," a general-purpose timer module, and a "computer operating properly/real-time interrupt" module (COP/RTI). The COP/RTI module provides two separate functions: a watchdog-like timer and a periodic interrupt generator.

As of October 1998, quantity 10,000 prices for DSP568xx family members range from $6.00 to $10.00. A complete analysis of the DSP568xx, including BDTI Benchmark™ results, is contained in BDTI's report, Buyer's Guide to DSP Processors, 2001 Edition.

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